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Upcoming 3D Integration events & Issues with the ITRS 3D Roadmaps
September 11, 2008
November a hot month for 3D Integration
RTI 3D Conf Nov 17-19
A few blogs ago I gave you a sneak preview of what’s going to happen at the RTI 3D Conference in the valley. The full program is now uploaded, but I wanted to specifically highlight the panel sessions. After the normal “where is the market” presentations by TechSearch [ for full disclosure I’ve told you before that I work on 3D market forcasts with TechSearch and co-author their 3D reports] and Yole, we have set up a panel session entitled “Examining commercialization…” where you will get to ask questions of Jan and/or Eric and representatives of Micron, Amkor, Tezzaron and (ex) Samsung. Most of you know that Yole has been far more aggressive in their market numbers than TechSearch so this should be very interesting. If you all don’t come up with the challenging questions, believe me I will.
Panel session #2 will look at process and tool options by Alcatel. Semitool, Brewer, XSil and EVG, basically the EMC3D consortium folks. We should expect an update on where they are and then we'll get to grill them on their process choices and their most recent claims that they can now achieve 3D integration for < $200 / wafer.
Panel session #3 we will do the same thing with Nexx, STS and Suss ( what I have called the “consortium with no name”) Are they ready to announce their group plans yet ??? Just maybe they will do it right here ??
Another tidbit on the upcoming presentations at the RTI 3D meeting. I’m told Ziptronix, the original 3D startup [ full disclosure thing again] will be revealing the keys to their patented DBI technology at this meeting [ see PFTLE 5/28/2008 “roadtrip continued”]. You’ll be seeing it here first in PFTLE and in a print article for Semi Int right before the meeting. Come on….tell the truth….. you are interested to know what Paul Enquist’s “magic metal” is !
IMEC 3D Intergation Workshop
Another major forum for November 3D activity will be the IMEC sponsored 3D integration workshop in Hsinchu on Nov 13-14th [check out PFTLE 2/26/2008 “IMEC setting up shop in Hsinchu”] IMEC has been a lead player in 3D technologies for years and my good friend Eric Beyne is one of the first people I e-mail when I have technical questions that I cannot answer.
Unfortunately this is back to back with the RTI conference and Garrou doesn’t do the back to back global trips anymore even in 1st class.
It’s IMEC’s goal to get some standards and roadmaps going to help us all along the way to 3D commercialization. This is a worthy effort and this is a group that can pull it off, but next year I hope there is some coordination with the timing of these 2 events.
Beware the Aspect Ratio
Privately, several of you have mentioned to me that I should keep up the “full court press” on the aspect ratio issue because that and “bonding throughput” are they key issues for 3D commercialization. Those of you that have been paying attention here at PFTLE, know that I go off on a Dennis Miller rant when I see tool vendors feverishly working on TSV with AR 10:1 and greater but cannot point to the short term applications that will need such high AR TSV. In previous blogs [see PFTLE 34 “If its Thursday it must be San Jose” ] I have gone through the major 3D Integration market segments and shown that short term (next 7 yrs or so) there is no major application that needs AR > 5.
I have now taken a look at the 2007 “Interconnect” and “Assembly and Packaging” ITRS roadmaps and have found the culprit ! I must admit I have stayed away from the Interconnect roadmap ever since they published their low-K roadmaps which over and over and over again promised low-K was just around the corner (which it never was). As you can see in the figure below the Dk of 2.5 that was promised in 1997 for 2001 by 2004 was being promised for 2011 (hey whats 10 years among friends).
In the end a roadmap is only as good as the input that creates it and back then, in my opinion, the input was coming from comittee members in the materials industry ( we had a few of them back where I used to work) NOT people who had any history in IC manufacturing. Obviously not everyone on the committee, but some.
Anyway – back to 3D and the present – the 2007 “interconnect” roadmap is shown below and you can see that in 2007 (year of production) they are claiming via diameter of 1.6-2.5 and max layer thickness of 7-25. If I take the max in both cases i.e. TSV dia 2.5 and Si thickness 25 that certainly is AR = 10 but the problem is that no one, no where on the face of this earth, has that in “production” for 3D Integration. It appears the “Assembly and Packaging “ roadmap folks just copied this number adding in a footnote “ ** This applies for small diameter vias. Larger diameter vias will have larger AR”. I have been asked my input for the 2008 “Packaging and Assembly” roadmap, which, you can be sure, I’ll be giving.
To clarify my position, one more time, I certainly see AR = 10 when the industry is manufacturing
1 um (vias first) TSV in 10 um of SI, but that will not show up in production till we are repartitioning chips and that will not be around ( read in production) before 2015. If we are going to get this 3D juggernaut into commercial production before then, I suggest we keep focused on the shorter term issues…….but that’s just my opinion, I could be wrong !
Coming up in future PFTLE blogs…….
…….Besang – claims “ First 3D Chip Manufacturing Process Developed”
……Semitool & EMC-3D - 3D processing cost under $200 per wafer
…….Ziptronics – the inside scoop on the DBI process
For all the latest on 3D IC Integration and other state-of-the-art microelectronic developments stay linked to Perspectives From the Leading Edge (PFTLE)……
Posted by Philip Garrou on September 11, 2008 | Comments (0)
