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....on Mechanical Bulls, Rollercoasters and CIS with TSV
September 26, 2008
Buckle up the ride is about to begin
Gilleys was a honky-tonk located in Pasadena, TX. Back in the early 1980s, after the movie Urban Cowboy made Gilleys infamous, my comrades and I would always make a point of ”doin’ Gilleys”when we visited Dows production facility in Freeport TX. It was the mechanical bull, not the line dancing or the Lone Star beer that drew me. Truth be told the only thing I compare to this ride was the Cyclone back in Coney Island (in NYC where I grew up). In both cases all you could do once the ride started was fasten your restraints, hold your breath, and “go with it”.
The microelectronic equivalent of those rides, for me, was when wafer level packaging took off, now a decade ago. Those that were in production first with this small form factor package, like National Semi, caused a shock wave in the industry. In the next 12-18 months every one of their competitors were forced to come up with the same technology / package form factor or lose market share. For a materials supplier, supplying a key material to this technology, these were glory days !
PFTLE has had many posts in the last year detailing how Toshiba, Oki, Aptina (Micron) and ST Micro have put capacity in place for CMOS image sensors (CIS) with TSV and how this was sure to be the first wave of the 3D Integration evolution. Well recent headlines continue to support this premise and lead me to conclude that we are about to enter the same “mechanical bull / roller coaster ridin” / phase for CIS with TSV. So my advice is buckle up and enjoy the ride !
Aptina adding suppliers ?
On Sept 5th Digitimes reported that Aptina (the Micron CIS spin put), although currently able to satisfy market demand, would be facing a capacity shortage in the next few quarters due to the demand for its new products with TSV. The report indicated that TSMC was a strong candidate to become the new outsourcing partner.
On Sep 15th came the headline from Chipworks that they had done a full reverse engineering on a mobile phone and had discovered an image sensor module, produced by Toshiba, using TSV technology. (Anyone who has access to this report and can give me further details please make contact with me)
Samsung CIS with TSV
On Sept 16th came the Digitimes headline “Samsung introduces CMOS image sensor dies to compete with OmniVision”. Samsung Electronics, who is now shipping CIS die to its customers ( allowing them to make camera modules by adding a controller IC to complete the camera module without subcontracting to a packaging company) announced additional CIS production capacity. According to Digitimes, Samsung's new products are produced using TSV. Since the other major players have already gone in this direction, it only makes sense that Samsung had to follow ( just like WLP). Remember the next technology implementation that will sweep through the image sensor market will most assuredly be BSI (backside image processing) which PFTLE described for you a few weeks ago [ “Backside Illumination Architecture for Next Generation CMOS Image Sensors”, PFTLE, Aug 3rd 2008].
3D / TSV Headlined at Semicon Taiwan
I hear that Semicon Taiwan was also “abuzz” about 3D IC technology. Rohm & Haas management indicated that they are hearing that many customers will begin to introduce TSV in the 32/22 nodes. KLA Tenkor indicated that their recent acquisition of ICOS Vision Systems included optical inspection solutions developed for TSV and that was one of the reasons for this acquisition. The Digitimes headline coming out of Semicon Taiwan , “Moore's Law takes a backend seat; TSV is the next battlefield” is a powerful statement of where things are evolving to in this field and is a worthwhile read.
Although the Digitimes write up worries about fabricating and filling high aspect ratio vias (which you know I am not a supporter of) they offer this comment which I fully support “..... it is via first – due to its intrinsically higher I/O opportunity (and hence the opportunity to keep on Moore's law without necessarily achieving device shrinkage) – that many players in the industry see as the holy grail. It is the most attractive 3D IC application to the design houses, and thus a higher value add proposition to the IDMs. Via first will probably be implemented by foundries and IDMs but not by packaging houses.”
coming in future PFTLE blogs:
........Semitool discusses the new < 190$ / wafer COO developments at EMC-3D
........Ziptronics begins to “open up the kimono” on their DBI process and exactly how it will lower COO for high density TSV processes
........will flash based storage replace hard disk drives ? will TSV memory stacks make this a reality ??
For all the latest on 3D IC integration stay linked to
Perspectives from the Leading Edge............
Posted by Philip Garrou on September 26, 2008 | Comments (0)
