It must be nice for those of you living in the Bay area where conferences on every microelectronic topic imaginable are held on an almost weekly basis. Not so for those of us living in the rest of the country. A few weeks ago SMTA held their second 3D, SiP Conference in RTPNC, right here in my back yard. I thought I’d share some of the interesting things that were presented.

Biao Cai of IBM gave a presentation on trends in DRAM packaging for Servers. His key points were:

• Memory capacity growing at minimum 2X per generation
• Memory performance growing at minimum 3X every 3 years
• DRAM technology scaling approaching fundamental limits
• System volumetric space allocation for memory approaching physical limit

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At the recent TSMC “open innovation platform” meeting they described among other things their plans to “…collaborate in the early stages of the IC design process” with their customers. My personal interest lies more in the details they disclosed about their plans for post back end of line activity. According to TSMC's new roadmap, the company is putting more resources into two areas: stacked die packages and 3D.

This announcement should be of concern to the contract assembly and test houses (Amkor, ASE, SPIL, STATS ChipPAC, etc. since such an expansion of services by TSMC will mean a potential loss of business for these assembly houses. While it is unlikely TSMC will produce stacked packages, TSMC has already developed 65-nm wirebond and flip-c...Read More

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By now, if you’re a reader of this blog, you know that I am preaching that 3D IC intregration will happen in an evolutionary not revolutionary fashion (which is how all things have happened in microelectronics over the past 50 years.

We have mentioned several times that 3D process flows have three unit operations in common: (a) TSV formation; (b) thinning and (3) bonding. Since thinning has been optimized in numerous other applications, the infrastructure is currently focused on introducing TSVs and bonding into mainstream production. Bonding technology without TSVs has been introduced by Infineon and Sony and TSVs without bonding are being commercialized by the various image sensor fabricators that we have been discus...Read More

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Finishing up on my coverage of the 3D Integration technology from last months IMAPS Device Packaging Conference in AZ........

NXP Passive Integration Devices to contain TSV

Yannou from NXP (the Philips semiconductor spinout) gave a very nice presentation on their integrated passive technology which they call PICS (passive integration and connecting substrate). We are not talking about Imbedded passives which are passives buried in PWB layers, but rather thin film components similar to what ST Micro has been manufacturing for several years (and they call IPADs).

Their cap...Read More

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This week I’m continuing to share information from the recent IMAPS Device Pkging meeting that was held on the Ft. McDowell reservation north of Scottsdale AZ. Must be because of the time I grew up....but as I type Ft McDowell my mind begins to wander to those great late 1950s westerns .... MGM proudly presents ”Ft McDowell” starring John Wayne, Gabby Hayes and Rita Haywerth. Anyway back to technology......

IMEC

Before I get to presentations and rumors from the meeting I’d like to share with you a new process variation that has been developed by Eric Beyne and the other 3D researchers at IMEC. As you can see from the figure below they first bond th...Read More

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The casino was second rate, the food in the casino was third rate but the information on 3D IC integration was priceless. The IMAPS Device Packaging Conference, attended by well over 500 professionals, is now history. In the next few blogs I will go over some of the significant information gleaned from the presentations and the side conversations in the hall ways.

First lets start with CIS (CMOS Image Sensor) packaging. If you’ve been keeping up with these blogs you know that Toshiba, Oki-Zycube and most recently ST Micro have announced 2008 production capacity for this wafer level packaging technology which uses backside TSV. In my last blog I pointed out that ST Micro is a...Read More

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As we get older we begin to understand that most technological advances are made in an evolutionary, not a revolutionary manner. I would further contend that paradigm shifts are only seen in hindsight. When an industry, such as Microelectronics, is faced with technology that requires major changes, the industry is usually resistant, because it is extremely difficult for the in place infrastructure to adjust and accept. Like the turtle, slow but steady progress always ends up winning the race.

When it comes to 3D IC Integration, we are currently involved in part of the larger merger, or blending, of packaging technology with on chip BEOL interconnect technology. I predict that 20 years from now technologists will look back and see this era as the one in which packaging and on ...Read More

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ST enters CIS camera market place with 3D TSV technology

ST's claims its latest 2M pixel mobile-phone camera module VD6725 is the worlds smallest single-chip camera sensor for mobile applications.

The VD6725 is available in ST's TSV (Through Silicon Via) wafer-level package, which enables the production of reflowable camera modules. These are soldered directly on the phone motherboard, which saves cost, space and time compared with the process of fixing traditional camera modules in the board socket. ST is one of the very few companies that have reflowable camera modules in production. Volume production is scheduled for the end of June. Unit pricing is in the $2 range, depending ...Read More

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Hsinchu

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There will be a major presentation by XSil at the upcoming IMAPS Device Packaging meeting in Phoenix in March. In keeping with Semiconductor Internationals goal of getting you all the leading edge 3D information as soon as possible in this Perspectives from the Leading Edge blog, I”ll give you a taste of what to expect in the following paragraphs.

Without question the author / presenter Alexey Rodin is one of the world experts in using lasers for 3D TSV processing. We have previously noted that Alexey and XSil were making some significant advances in laser processing with vias down to 10 microns now possible (Perspectives From the Leading Edge - "Going Verticle in Whitefish" - Sept 9th 2007). Being maskless, the laser process obviously elimin...Read More

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Down here in Research Triangle Park NC it’s hard to believe that it’s early February. It’s been in the low 70’s which is about 25 degrees above normal. If this is an indication of global warming, we are all in trouble and I’ll be looking for land next summer in Maine......... I always did love Ogunquit. On the microelectronics front, nothing remains hotter than 3D.

For those looking for an equipment this auction announcement out there: http://www.thebranfordgroup.com/DNN3/Auction/CUBI2.aspx listed as “complete development facility closure”. Cubic Wafer has not updated their web page since Sept 2005......hummmm

Earlier in January In-Stat reported that the first product in the Intel Larrabee product family “...is ta...Read More

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As I’ve mentioned before when it comes to really knowing what’s going on in the microelectronics industry there are only two knowledgable sources –material vendors and equipment vendors.

Earlier this month I was able to interview Steve Dwyer, VP and GM of EVG NA and Thorsten Matthias, Dir of Technology, about their perspectives on the approaching commercialization of 3D IC integration.

Aside from being founding members of the EMC-3D consortium (see past blogs for details), EVG is supplying the following tools to the infant 3D marketplace: Smartview® aligner/bonder for wafer-to-wafer (W2W) technology, nanocoat spray coaters for coating surfaces with topography and they have joint programs with Brewer Science to supply to supply temporary bond / debonding technology and with Datacon to supply chip-to-wafer (C2W) bonding technology.

They...Read More

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