There was lots to be said about extreme ultraviolet (EUV) lithography at SEMICON West — some of it good, some of it not so good. On the one hand, Cymer announced that it would be ASML's EUV source supplier going forward. Along with that announcement, Cymer detailed the advances made in its laser-produced plasma (LPP) source design (Cymer switched from DPP to LPP three years ago). Cymer has managed to get IF power up to 50 W, which is significant progress in output power. And the lithography source manufacturer promises to reach 100 W by the end of the year (and, according to Cymer's Nigel Farrar, the company has hit every one of its marks since setting its roadmap at the beginning of last year). That's downright close to the target the industry has been aiming for to achieve production thro...Read More

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Double patterning has gone from the fall-back position for EUV to the front-and-center stage technology for extending 193 nm lithography. The speed at which flash devices are transitioning (now the minimum feature and pitch driver) means there will not be enough time to develop EUV for the 32 nm node. A few things need to happen to make double patterning a reality. Overlay is a big one. Having the necessary design tools in place is key too. But for companies that have already done double patterning for prototype devices, perhaps this transition will be slightly easier than, say, going to immersion lithography.

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After years of driving specifications for particles and other contamination to smaller and smaller dimensions, the industry is getting to a new level: If we can't measure it, we don't know if it's there. Somewhere around 40 nm, we can no longer detect defects, so rather than ask for better and better specifications from gases, chemicals and on wafers, we need to control the processes better. This is the gist of the new ITRS Yield session, which is being updated at the show today and will be revealed towards the end of this year. Big (or small) things may be in store.

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Digital circuitry – mostly processors and memory – will continue to scale according to the venerable Moore’s Law. But what about everything else where miniaturization isn’t the main driving factor? Things like analog circuitry (i.e., RF for wirelesss), sensors/actuators, passive components, high voltage devices and even bio chips. The need to integrate these kinds of functions was first mentioned in the 2005 ITRS, briefly in a couple of paragraphs. But the industry is now desperate to integrate all these kinds of functions on a single chip, perhaps through system on a chip, but more likely through system in package or, ultimately, 3D integration. The ITRS roadmappers are trying to call attention to this need for heterogeneous integration, using the catchy but only sl...Read More

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Rumor had it that there might be an announcement coming out of Sematech today on 450 mm wafers. This highly controversial topic may be the story that never was: at least, for 2007. The feeling we’ve gotten recently and also around the show, from tool manufacturers and even the majority of chip producers, is that 450 mm wafers simply are not a priority at this time. Making 300 mm wafer fabs more productive and cost-effective is a much more attractive alternative. There are really only three companies pushing the 450 mm question right now: Intel, Samsung and TSMC. While these companies together produce a lot of silicon, it’s not looking like they can get the rest of the industry on the bandwagon for now.

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Deep in the bowels of the Moscone Center is the Green Room, complete with make-up mirrors and a shower (don’t ask me why) and that’s where SI editors are ensconced, cranking out copy for the Show Daily, which we’re doing in conjunction with SEMI staffers this year. Best one ever if we don't say so ourselves. The overall mood at the show is fairly exuberant. Although equipment sales are expected to level of this year, 2007 will be the second largest year EVER for new semiconductor equipment sales. What’s a little different at this year’s show is an increased emphasis on what you might consider “non-mainstream” – that is not silicon-based CMOS tech -- such as photovoltaics and nanotech. More later!

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The editors of Semiconductor International have already been hard at work preparing for SEMICON West, to be held July 17-19 in San Francisco at the Moscone Center on 4^th Street. Our new partnership with SEMI (we’re now the “official magazine of SEMI,” as you’ve undoubtedly heard) has enabled several new opportunities. We’ll be producing the official pre-show planner, with schedules, maps, exhibitor lists, executive viewpoints and lots of other good stuff, which will be mailed to arrive mid-June. We’re also working with SEMI on a series of newsletters, the first of which went out May 4^th. You can sign up for the SI Weekly – which includes a weekly news update as well as Special Reports such as the SEMICON West series. We’re also goin...Read More

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