Technologists Assess 3D Interconnect Technologies and Equipment Readiness at SEMATECH Workshop during SEMICON West

A host of industry experts involved in the development and implementation of 3D interconnect technology gathered at a SEMATECH-led workshop to explore equipment challenges for 3D interconnect, comparing application requirements to those proposed by the International Technology Roadmap for Semiconductors (ITRS).

The workshop entitled "Equipment Challenges for 3D Interconnect," conducted on July 16th during SEMICON West, attracted approximately 70 IC manufacturers, equipment suppliers and industry experts. The goals of the workshop were to explore the challenges for making wafer processing equipment capable for 3D interconnects.

Presentations were given by technologists representing Qualcomm, EV Group, Accretech, Suss MicroTec, Sonix, NEXX Systems, and Applied Materials. Presenters focused on highlighting cost and performance challenges for the technology's viability, affordability, and schedule, including topics such as 3D lithography, wafer bonding/aligning, wafer polishing/grinding, 300mm bonded wafer metrology, 300mm wafer copper plating and 300mm wafer thru silicon via (TSV) integration.

"We are extremely encouraged that such high caliber companies and individuals participated in the event," said Sitaram Arkalgud, SEMATECH's 3D director. "Through SEMATECH's 3D Interconnect program and workshops such as this, attendees can compare progress and develop an assessment on integration approaches, process architectures, and tool sets that will make 3D-TSV commercially viable."

The 2007 ITRS roadmap forecasts high density TSV pitches ranging from approximately 4.5 microns in 2008 to approximately 2.5 microns in 2012. Through a panel discussion, the workshop provided extensive readiness assessments of 3D roadmaps and standards that are currently driving industry-wide initiatives. Specifically, although integrated device manufacturing participants acknowledged the ITRS density targets are aggressive, the equipment suppliers were generally positive about their ability to achieve these goals.

Andrew Rudack, SEMATECH's 3D equipment process engineer and workshop chair said, "We must have the 3D tooling infrastructure available, and address the equipment concerns that have to be resolved before volume manufacturing can take place."

SEMATECH's 3D Interconnect program was established to drive the semiconductor industry's most comprehensive investigation of the potentials of 3D interconnects using TSV. In effort to explore the different 3D options, including wafer-to-wafer and die-to-wafer integration, SEMATECH hosts a variety of forums and projects to help define and map 3D technology options, develop unit processes and metrology, and ultimately demonstrate 3D's manufacturability and reliability. To learn more about SEMATECH's 3D interconnect program and its upcoming meetings, please visithttp://www.sematech.org/research/3D/index.htm.

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