S KOREA DEVELOPS WORLD'S FIRST 3D CHIP MANUFACTURING PROCESS

South Korean engineers have developed the world's first three-dimensional integrated circuit (3D-IC) technology, an advance that should lead to greatly expanded computer chip capabilities, the government said Monday.

The technology, developed jointly by state-run National Nanofab Center and venture firm BeSang Inc., is noteworthy because it can overcome the physical limits of enhancing integration of existing two-dimensional complementary metal oxide semiconductors (CMOS), the Ministry of Education, Science and Technology said.

CMOS technology is used to make microprocessors, microcontrollers, and various digital logic circuit chips that form an integral part of all information technology devices.

"Because of the limits associated with two-dimensional semiconductors, skyrocketing costs and manufacturing difficulties, engineers have been trying to find a way to stack ICs for several years without success," said a engineer at the Nanofab center.

He said the new system that links ICs with so-called single crystal silicon substrates overcomes the limits of existing "multi-chip packages" that rely on inefficient wire bonding techniques to connect stacked chips that are used in through silicon via (TSV) devises.

"Unlike the multi-chip packaging method employed in TSV, the new system allows for almost limitless number of vertical connections linking stacked chips," the expert said. The engineer added because the manufacturing process can take place at under 400C compared to 850C for current operations, there is no worry of ICs being damaged while they are stacked on top of each other.

A further advantage of the new technology is that since there is no pressing need to strive for greater integration on a two-dimensional level production cost can be controlled and brought down.

Manufacturers have complained that buying new manufacturing equipment was becoming prohibitive with the advent of new chips that required every greater integration levels.

The use of 180 nanometer CMOS manufacturing technology that are in wide use today and conventional 8-inch silicon wafers is also a plus in keeping prices down.

Industry sources said that because the new system can bring about an unprecedented degree of integration, with a negligible increase in size, it can be used to make advanced memory arrays, image sensor photodiodes systems on chip and microprocessors.

The state-run laboratory has requested three patents while BeSang, a U.S. venture tech company owned by a Korean businessman, holds three basic technology rights and is applying for 25 related patents.

Commercial production can take place relatively quickly once engineers design chips to meet specific product requirements and necessary manufacturing tools are made.

(Yonhap)