3-D, TSV Need Standards and Thermal Solutions to Advance
Yesterday's sessions at the 3-D Architectures for Semiconductor Integration and Packaging conference indicate that although the technology is progressing and coming into use, there still are unanswered questions about practical, real-world, high-level applications.
Alexander E. Braun, Senior Editor -- Semiconductor International, 11/19/2008 7:46:00 AM
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Michael Shapiro, 3-D chief technologist of IBM’s Systems and Technologies Group (Hopewell Junction, N.Y.), views 3-D integration as even more revolutionary than the shift from aluminum to copper interconnect. “It’s increasingly difficult to increase semiconductor performance; it’s harder and harder to overcome the obstacles that we’re encountering, and 3-D has at least the potential to surmount many of these roadblocks,” he said.
In his presentation, “3-D Technology: Applications and Requirements,” Shapiro outlined four drivers important to 3-D development, the first being bandwidth. He pointed out that clock frequency started to flatline in 2004, when it began becoming difficult to push increasingly smaller transistors into faster operation by boosting power; this caused microprocessor speed to begin leveling off. The solution was the use of multicore processors to raise performance independently of power. However, this is a stopgap measure, because as the number of cores increases, I/O limits will eventually data-starve processors. “Here, 3-D can help by increasing bandwidth by stacking chips — no interconnect or packaging limits — making it possible to eventually go to 100,000 signal I/O, breaking the bandwidth wall,” Shapiro said.
The second driver is power reduction. Power not only limits clock speeds, but also affects I/O. Now the focus is on getting higher bandwidth on and off chip by making the I/O drivers and receivers go faster, driving power. “Here, 3-D can help by providing shorter lines with lower I/O swing, reducing drive strength,” Shapiro said. “It can provide wider and slower buses that reduce switching power, and eliminate I/O for multiple chips in a stack.”
The third and fourth ways are form factor, which provides higher density by stacking and/or integrating system components in one package, and modularity, which permits separating IP macros (memory, analog and logic) onto different layers, as well as the reuse of IP in new applications.
“There still are challenges,” Shapiro warned. “If 3-D is to progress, EDA software must be developed and inspection and test solutions be found. There are thermal interface problems, warpage, chip packaging — you name it — all of which must be solved as a suite to make the technology real.”
Shapiro added that through-silicon vias (TSVs) have their own reliability requirements. “Early applications may have more than 100,000 TSVs on a wafer. If you have 99.5% yield, your entire wafer could be scrap. Considering that future applications will drive well over 10,000 TSVs per chip, it’s clear why the TSV process must be bulletproof. Of course, the question is how do you test 10,000 TSVs to ensure they work?”
There is a tremendous need for 3-D standardization. Customers, suppliers and EDA vendors realize that a common TSV integration approach is essential. Otherwise, expenses and product costs cannot be minimized — there will be no predictability for tool and process requirements, no common design methodology and inspection and test specifications, and no portability for end manufacturing. “Currently, 3-D standardization is in its Wild West phase,” Shapiro said.
Shekar Borkar, an Intel Fellow (Santa Clara, Calif.), focused on a system perspective for 3-D technology. Today, at the 45 nm node, 8 billion transistors can be integrated on a die, he said, and in a decade we can expect a capacity of about 100 billion transistors. This raises concerns about the die’s thermal condition. Scaling projections show that around 2018, power will be too high, limiting frequency and size. Such a die would have 600 W of total power consumption — an obvious impossibility.
Thermal considerations may be such that 3-D integration of high-performance logic for higher integration may be impractical. One proposed solution considers new thermal architectures. “We may need dedicated thermal TSVs,” Borkar said. “These would be large, approximately 100 µm in diameter and 200 µm deep, and filled with copper to provide adequate thermal paths.”
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| The integration of 3-D technology may require dedicated thermal TSVs. These would be large (~100 µm in diameter, ~200 µm deep), and use copper to provide the thermal paths. (Source: Intel) |
The subject of “3-D TSV Interconnects: Technologies, Markets, Players” was covered by Jeff Perkins, an analyst at Yole Développement (Lyon, France), who observed that since 2007, TSV has become a reality in CMOS image sensors. Toshiba (Tokyo), Samsung (Seoul, South Korea) and STMicroelectronics (Geneva) use them for camera cell phones, and he expects at least five new players by next year.
According to Perkins, MEMS 3-D stacked memory is a reality, with first DRAM production scheduled for 2009, with at least one of the memory players in production. “At first volumes will be small,” he said, “in the range of approximately 100,000 wafer starts per year.” He added that there will be a high-growth ramp-up during 2010-2011. In 3-D logic system-on-chip (SoC) and system-in-package (SiP) devices, wireless logic — baseband applications — first products should appear by 2010, with microprocessor and memory stack coming later, Perkins noted. “FPGAs will come later too,” he said, adding that 3-D substrates such as silicon interposers are also being actively developed.
Perkins does not view the current economic turmoil as overly affecting things like 3-D IC packaging with TSV. “We believe that 3-D investments are strategic innovation and as such will continue even during difficult times,” he said. “The adoption of TSV opens up a new integration era and a possible supply chain value change for all players, as value migrates to the package. IDMs, MEMS manufacturers, wafer foundries, packaging houses and OSATs are all poised to go, but new investment and learning will be required.”
