Can We Afford High-k for III-Vs?

It is getting harder to wring performance gains from silicon, even as the transistor size is made smaller. That trend leads to an intensifying debate about whether III-V transistors will augment silicon in performance-driven applications.

A few iconoclastic researchers have long questioned the cost benefits of the III-V research effort. At Sematech's International Symposium on Advanced Gate Stack Technology (ISAGT) in October, outgoing Sematech high-k program manager Byoung Hun Lee privately raised the issue of whether the chip industry has the money to take III-Vs to the finish line.

Lee, who was assigned to Sematech from IBM, is returning to his native South Korea to teach at the Gwangju Institute of Technology, and he has a specific research goal in mind: to investigate nanoelectro-mechanical systems (NEMS) switches that could be used on silicon ICs to help control power. Developing low-power techniques for silicon chips should receive a much higher priority from the research community than now, he argued.

At ISAGT, Lee said IBM and Intel each spent more than a billion dollars on high-k R&D over more than a decade. Although the high-k effort for silicon was well worth it, similar amounts will be needed to develop a workable gate oxide for III-V-based devices, which would have a much smaller market window, he said. "Do companies have another billion dollars each to solve the high-k problems with GaAs technology?" he asked, noting the tighter profit margins prevailing now.

Lee was not the only dissenting voice at the symposium. A prominent Taiwan-based professor voiced similar sentiments, saying the chip industry would be much better off to put its R&D resources into silicon-based development. III-Vs "will never make it," the professor said, because of low effective mass, narrow bandgaps, and defect densities, among other reasons. (He asked not to be quoted by name because "so many of my friends are being funded to do III-V research.")

The reality is that it is tough to get funding for silicon-related research now. If a researcher has, for example, graphene-based electronics as a research topic, federal money flows more easily. And the bullish prospects for carbon nanotubes (CNTs) as interconnects, where many of them can be bundled together into fast wires, is another relatively well-funded research area, and deservedly so.

Eric Vogel, an associate professor at the University of Texas at Dallas, spent a decade as a staffer at the National Institute of Standards and Technology (NIST, Gaithersburg, Md.) before going to work at UTexas, where a high-vacuum deposition chamber is in operation for world-class III-V research. Vogel said the widespread use of SiGe epitaxial deposition techniques to create strain on the silicon pFET channels has given the industry some confidence that it can create heterogeneous CMOS, with germanium used for the pFETs (taking advantage of the relatively high mobility in germanium) and III-V films deposited for the nFETs.

The bulk mobility of In_0.53Ga_0.47 As at a doping density of 10¹⁷ cm^-3 is ~6000 cm²/Vs, Vogel reported in an invited paper at the gate stack meeting. However, not everyone is convinced that the ~10× increase in mobility that GaAs nFETs enjoy over silicon will translate into sharply higher drive currents, due to the lower effective mass of the electrons. And density defects, material costs and other important factors must be taken into account.

The biggest challenge is to identify a high-k dielectric for III-V transistors. "It took four or five years in silicon to narrow down the high-k options to the hafnium-based materials," Vogel said. "For III-V dielectrics, we are at about the same place now that silicon was at in 1997–98." To some extent, the knowledge gained during silicon high-k development can be applied to gallium-based nFETs. Also, the experience with atomic layer deposition (ALD) tools will carry over to the III-V development effort, he said.

Research money is shifting to germanium and III-V transistors, to graphene, CNTs and spintronics. That is well and good, as research should have an over-the-horizon view. And high-k research for III-V transistors has made enough progress in the past few years to deserve continued funding. That said, given the cost constraints of the consumer-use chips that make up an increasingly large share of semiconductor revenues, improvements in basic silicon technologies, including power-savings approaches such as those being pursued by Lee, should not be given short shrift.