Self-Aligned Double Patterning Coming
Applied Materials Inc. (Santa Clara, Calif.) announced several new tools at SEMICON West, and said that its self-aligned double patterning technology is gaining acceptance at key NAND flash manufacturers.
David Lammers, News Editor -- Semiconductor International, 7/17/2008 8:00:00 AM
With an eye on the large but cost-sensitive memory IC market, Applied Materials Inc. (Santa Clara, Calif.) announced several new tools at SEMICON West, and said that its self-aligned double patterning (SADP) technology is gaining acceptance at key NAND flash manufacturers.
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| Jen Shu, Director of Technologies, Maydan Technology Center, Applied Materials Inc. |
“Anything beyond 40 nm for NAND — the 3x and 2x generations — needs to use double patterning,” she said, noting that both Samsung Electronics Co. (Seoul, South Korea) and Hynix Semiconductor Corp. (Icheon, Korea) announced last year that they would use SADP for their 3x generation NAND flash. Also, the 34 nm NAND flash recently announced by the IM Flash Technologies (Lehi, Utah) joint venture between Intel Corp. (Santa Clara, Calif.) and Micron Technology (Boise, Idaho) uses a spacer type of technology, she said, citing reverse engineering analyses of the IM Flash devices.
“We demonstrated this technology a year ago, and now we are working on the manufacturing productivity. Every tool must have a higher throughput and better performance to really cut it in volume production,” she said. Also, the line edge roughness (LER) and linewidth roughness (LWR) require improvements, she added.
Tantalum to titanium shift
As memory manufacturers adopt copper interconnects initially for the bit-line interconnect layer, equipment vendors are responding. Jim van Gogh, general manager of Applied’s copper, PVD and integrated systems group, introduced the Applied Endura Extensa PVD tool at the show, featuring a dual-magnetron architecture. The second magnetron is primarily used for cleaning to ensure a very clean target surface during titanium and titanium nitride (TiN) deposition.
Van Gogh said memory manufacturers seek to use a titanium barrier layer, rather than the more expensive tantalum, to reduce costs. Some customers are still using tantalum, but want to migrate to titanium because the metal itself is less expensive. “Most people are just converting the M1 bit-line layer. Having both copper and aluminum layers in a hybrid approach creates the need for titanium,” he said.
With cost as their key focus, memory manufacturers are emphasizing throughput and cost-of-ownership (CoO). The Extensa tool is able to run for a long time without target changes. “The Extensa can do the equivalent of 8000 wafers with 400 Å titanium and titanium nitride deposition. It has a very low cost of consumables, while still providing high throughput of 30 wafers per chamber,” van Gogh said.
"Applied also introduced the Producer etch system aimed at interconnect etch for flash and DRAM memory devices. Again, cost and throughput are the drivers, said Kathryn Keswick, technical marketing manager for the etch products business group. “There is a paradigm change going on because everybody is more cost-sensitive. Our customers are driving us to lower costs for operating the tools,” she said.
Uday Mitra, CTO for the etch group, said the Producer has six chambers in a small throughput. Two chambers flank a common gas panel, for example, which improves the CoO.
Applied also unveiled the eHARP for shallow trench isolation at and beyond the 32 nm node. Ajay Bhatnagar, a manager in the gap fill dielectric division, said aspect ratios are trending toward 12:1 and CDs to 30 nm, “which is a challenge for filling. The eHARP system extends the process capabilities of the earlier tool with a novel approach to how the ozone TEOS materials reach the vapor injection system."
