TSMC Readies 40 nm Process Technology
Staff -- Semiconductor International, 3/24/2008 9:41:00 AM
Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC, Hsinchu, Taiwan) unveiled a 40 nm linear shrink of its 45 nm manufacturing process technology in both a performance-driven, general purpose (40G) version and a low-power (40LP) flavor. Production is expected to begin in the second quarter of 2008.
Compared with the 45 nm LP process unveiled last year, the 40 nm LP technology reduces power scaling by ~15% and is aimed at wireless and portable devices.
The 40 nm technology’s raw gate density is 2.35× higher than the 65 nm process, with an SRAM cell size that TSMC claims is the smallest in the industry (0.242 µm2).
The 40 nm logic family includes a triple-gate oxide for wireless and portable applications that require low-power operation as well as high levels of performance. Both the 40G and the 40LP processes offer multiple threshold voltages and 1.8 V and 2.5 V I/O options.
“Our design flow can take designs started at 45 nm and target them toward the advantages of 40 nm,” said John Wei, senior director of advanced technology marketing at TSMC. “A lot of TSMC development work has gone into ensuring that this transition is truly transparent. Designers need only concentrate on achieving their performance objectives.”
A full range of mixed-signal and RF options are offered, and multi-product wafers will run in the company’s shuttle service starting in April. “Dozens” of customers are in the design phase, the company said. The 40G and LP processes will initially run in TSMC's 300 mm Fab 12 in Hsinchu, and will be transferred to Fab 14 in Tainan as demand ramps.
The technology portfolio features a full design service package and a design ecosystem that covers verified third-party intellectual property (IP), third-party EDA tools, TSMC-generated SPICE models and foundation IPs, the company said.
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