IBM Alliance Develops 32 nm High-k/Metal Gate SRAM
David Lammers, News Editor -- Semiconductor International, 12/9/2007 9:01:00 PM
IBM Corp. (Armonk, N.Y.) said today it has developed a test SRAM array using 32 nm high-k/metal gate (HKMG) process technology, an achievement that puts IBM and its Fishkill alliance development partners on track to introduce 32 nm technology in the second half of 2009.
Gary Patton, vice president of IBM’s Semiconductor Research and Development Center in Fishkill, N.Y., said HKMG technology will become available not only to the Fishkill alliance development partners, but to fabless design teams that use one of the alliance partners to foundry their 32 nm designs. IBM plans to accelerate introduction of the 32 nm process, making it available to its foundry partners within a quarter of IBM’s own schedule.
“Both Intel and IBM have talked about using high-k 45 nm technology to produce their own parts,” Patton said. “What is significant about this announcement is that, through the partners and foundries, 32 nm high-k technology becomes available to the wider industry for the first time. Design teams can start the whole design planning process now.”
The 32 nm project team fabricated the 1.5 MB array very recently, with first-pass success, said An Steegan, the 32 nm bulk CMOS project manager. The cell size was described as <0.15 µm2, half the cell size of the 45 nm SRAM cell size.
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| Pictured (left to right): Craig Lage, project leader: Freescale; An Steegen, project manager, 32 nm bulk technology, IBM; John Pellerin, project leader: AMD; Ja-Hum Ku, project leader: Samsung; John Sudijono, project leader: Chartered; Mukesh Khare, project manager: high-k/metal gate technology, IBM; Richard Lindsay, project leader: Infineon; Effendi Leobandung, project manager: 32 nm SOI technology. |
“Variability improves because of the use of high-k,” Steegan said. With the scaled oxides, the gate dielectric was so thin that leakage and variability issues were troublesome. “The use of high-k means that in terms of variability, we do not have too many more worries at this stage.”
Patton said the 1.5 MB array is what IBM will use very early in the development process, adding, “We will go to a much larger-sized array soon.”
IBM and Advanced Micro Devices (AMD, Sunnyvale, Calif.) separately are developing a silicon-on-insulator (SOI) 32 nm technology, based on the HKMG gate-first solution developed for the 45 nm generation. Patton said IBM will use the SOI 45 nm process for IBM’s proprietary products, and will offer a non-high-k 45 nm process to its foundry and OEM customers.
The bulk 32 nm development partners include AMD, Chartered Semiconductor Manufacturing Ltd. (Singapore), Freescale Semiconductor Inc. (Austin, Texas), Infineon Technologies (Munich), Samsung Electronics Corp. (Seoul, South Korea), and — the most recent addition — STMicroelectronics (Geneva).
The announcement was timed to coincide with the opening of the International Electron Devices Meeting (IEDM) in Washington, D.C. Patton said the SRAM array was fabbed too late to be submitted as an IEDM paper. Instead, IBM will present its 32 nm technology at the 2008 Symposium on VLSI Technology, planned for June in Hawaii. The IBM announcement will allow the Fishkill alliance technologists to talk up the 32 nm technology to the other participants at IEDM, Patton said.
Intel is set to disclose some details of its 45 nm HKMG technology on Tuesday at IEDM, and the IBM announcement, while not an IEDM paper, is sure to compete for headlines with the Intel disclosures in Washington.
The low-power (LP) process will be introduced first, using a 1 V operating voltage, followed by more leaky, higher-performing transistors. The 32 nm HKMG transistors deliver a 45% total power savings, and up to a 30% higher performance compared with the previous generation. “Performance absolutely is improving — there is no question in our minds about that. We use a range of benchmarks to measure performance at each technology node,” Patton said, adding that PDAs and cellphones require higher densities and faster chips, as well as lower power. “With HKMG, there is no question they will be able to get much better performance, in part because of the higher density.”
Mukesh Khare, project manager of HKMG technology at IBM, said the Fishkill alliance’s hafnium-based gate-first process can withstand subsequent high-temperature process steps better than Intel’s gate-last approach. He said that will make it easier for customers to move to the 32 nm process. “We focused on the materials aspect so we could insert HKMG into a conventional flow,” he said. “We sought to use materials capable of withstanding conventional high-temperature processing. That supports an ease of integration, with no additional design restrictions, which opens it up to partners and fabless companies.”
Kaizad Mistry, an Intel vice president and director of logic technology integration, said IBM’s 1.5 MB array compares with a 36 MB array that Intel introduced in September at the Intel Developers Forum. The Intel SRAM has a 0.18 µm2 cell size.
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| Intel's 32 nm test chip, unveiled in September, has PLLs and other test circuits on board. |
“One of the things we’ve noticed over the years is that companies publish SRAM cells at IEDM. Then you look at their products a couple of years later, and find that when it comes to products, it is a different cell, a bigger cell. The Intel array we discussed three months ago is what we plan to use for our products,” Mistry said.
Richard Doherty, an analyst at The Envisioneering Group (Seaford, N.Y.), said IBM came out with its press release in part to steal some thunder from Intel’s IEDM 45 nm presentation. “The work behind this [IBM 32 nm SRAM] is not rushed out, but the timing [of the announcement] certainly is. This shows there are other spotlights besides Intel’s. Nobody can outspend Intel in terms of semiconductor research, or in the candle power of its public relations. This announcement shows that IBM believes they have a lot of tricks they can implement.”
Doherty said the IBM alliance represents Intel’s competition. “I love competition,” he said. “It tends to bring out the best in the lab guys. Otherwise, they might not finish their projects.”
