Metrology Drives Nanotech Progress

In a conference presentation,¹ Mark Durcan, president and COO of Micron Technology (Boise Idaho), outlined some of the challenges nanotech faces. While admitting that progress was taking place, he also warned that there are many difficulties, such as randomness issues associated with dealing with large and small numbers, mechanical issues at small dimensions, and increasing difficulties of patterning and metrology.

More resources needed

Ahmed Busnaina, director of the National Science Foundation (NSF) Nanoscale SciWence and Engineering Center for High-Rate Nanomanufacturing and the NSF Center for Microcontamination Control at Northeastern University (Boston), pointed out that nanotech progress is not at the level predicted three years ago. "Some of the carbon nanotube non-volatile memory work hasn't developed as expected. Phase-change memory is advancing, but mostly using traditional semiconductor manufacturing technology. Assembly technology hasn't evolved as fast." Busnaina admitted that unexpected problems arise when working in a new field, and that learning is taking place. "CNT discoveries take place almost daily on assembly control, measurements, etc. At the same time, great strides are being made in large-scale directed assembly of carbon nanotubes and nanoparticles for electronic applications."

Busnaina believes that nanotechnology research needs more resources, certainly in nanomanufacturing and the development of new materials. NSF spends ~$300M on nanotech and partners with Semiconductor Industry Association (SIA, San Jose) in a $2M fund for nanoelectronics. The industry's contribution is minor by comparison, plus semiconductor companies no longer do as much research as they once did. The few companies that still do, such as IBM (White Plains, N.Y.), Samsung (Tokyo) or Intel (Santa Clara, Calif.), have relatively small efforts; more is being done by academia. It is not enough for the industry to just invest more; it must also partner with academia. "There's an awareness of the difficulties to be encountered in 2015 or 2020, but they're years away and the industry is confident — one might say overconfident — about its capability to produce workarounds, although these are getting more expensive and the returns are getting smaller," Busnaina said.

The litho question

Like others, Marc van Rossum, advisor for the Strategic Development Unit at IMEC (Leuven, Belgium), views nanoelectronics as a means to buttress silicon. However, for him, the major problem is next-generation lithography. "We reached the 45 nm node on schedule because current litho techniques could be stretched," he said. "Somewhere between the 32 and 22 nm nodes, this will no longer work." Presently, there is no consensus on what the future lithography technique should be — 193 immersion or extreme ultraviolet (EUV) lithography. IMEC is doing preliminary EUV work with an experimental ASML (Veldhoven, Netherlands) EUV litho system, as is the University at Albany's College of Nanoscale Science and Engineering (CNSE, Albany, N.Y.). A prime objective is investigating resists suitable for short-wavelength lithography; there are serious sensitivity problems needing resolution.

"Lithography is crucial to scaling," van Rossum said. "At 22 nm, we'll need some form of nanolithography. Work should proceed not just on EUV, but alternatives such as super-high NA-value immersion, and also to improve nanoimprint lithography. The roadmap's continuity will be determined by the lithographies we develop and their cost."

New materials, measurements

Serge Oktyabrsky, a professor of nanoscience at the CNSE, sees a change in the industry's traditional reluctance toward new materials. "The industry isn't as afraid to look at materials other than silicon. Particularly with III-Vs, there are discussions about nanomaterials, molecules, CNTs, etc. This means two things. The first is that now the silicon era's end is foreseeable. Second, that silicon users will migrate to demonstrably scalable materials. There are many potentially better than silicon, which could be used for the next few generations."

From a physical perspective, considering silicon integration challenges for these different materials, there is no difference in making a device out of silicon or carbon nanotubes (CNTs). Silicon became king because of its excellent SiO₂ interface. Integration is less of an issue; more important is a scalable solution for a material, interface and structure that may be better than silicon or SiO₂.

Roger Stancliff, CTO for the Components Test Division of Agilent Technologies (Santa Rosa, Calif.), sees obstacles at 45 nm and beyond. "For CMOS, the scaling issues are leakage current, which drives high-k, because if the dielectric constant increases, one can have thicker dielectrics for the same performance and, thus, reduce leakage current. High-k presents measurement challenges."

Channel dimensions are also changing, affecting ion implantation and annealing, which locate the source and drain (S/D), and doping density and how doping travels in smaller dimensions. Anneal becomes more of a challenge, while gate length and gate quality become increasingly critical as they shrink. Another problem is cross talk and parasitics between devices as more transistors are put on a chip or wafer. Power dissipation is another hurdle, driven by parasitic resistances.

Then there are new materials that affect interface quality. "For 20 nm, people are considering putting GaAs and germanium on silicon wafers; build islands of optimized p and n channels," Stancliff said. "This will lead to measurement challenges related to these islands' interfaces and interactions. Scaling leads to higher impedance. We've seen an extreme case of this in CNT transistors being considered for beyond 22 nm; they have 10 to 100 K input impedances, and measuring them with a 50 Ω instrument is very difficult."

There are two ways to measure all this. One is using an atomic force microscope (AFM) with a microwave path down to the tip, and building a structure that measures capacitance with high sensitivity and accuracy — a resonant-mode microwave AFM instrument. This can also operate in a non-resonant mode, where one simply probes devices to measure their electrical characteristics (Fig. 1).

1. Using a very high sensitivity scanning capacitance microscope, it becomes possible to see semiconductors, insulators and conductors. In this comparison, on the left is a normal AFM topographical picture of a SRAM chip. On the right is the scanning capacitance image of the same chip. (Source: Agilent Technology)

The resonant mode provides other measurements. "You can get calibrated capacitance measurements, and you can put voltage at the tip and use it to control depletion depth to probe capacitance vs. depth," Stancliff said. Another option is doing leakage current measurements, which are important for dielectrics.

Topography measurements are also possible. "With topographical information, you can calculate the effect of a step on capacitance and get back to it as if you were measuring on a flat surface," Stancliff said. Before, tip availability made this difficult. Many AFM tips are created out of micromachined silicon and made conductive either through highly doped silicon (unsatisfactory) or by metallization, which wears off. "We came up with a new tip based on metal, working with a company called Rocky Mountain Nanotechnology (Salt Lake City). They built <10 nm tips, enabling resolutions in the order of half the tip's dimension." This meets an International Technology Roadmap for Semiconductors (ITRS) requirement for <10 nm measurements, even at the 45 nm node. Thus, there is the potential to non-destructively provide information about doping vs. depth, because depletion depth can be varied and the topography effect eliminated.

Silicon, spintronics

Vincent LaBella, leader of the CNSE's spintronics research, observed that since the early 1990s, people have thought about using the spin of the electrons for more than just data storage. "We're researching how to inject and detect spins in semiconductors," he said. "Most magnetoresistive devices are metal or oxide based. We want to combine them with semiconductors to do logic processing. With spin in a logic device, you can potentially achieve high speeds with lower power."

Silicon is the new spintronics material. It is one of the best semiconductors for this because it provides a long spin lifetime; spins travel coherently and remain coherent for almost a microsecond, practically an eternity compared with GaAs, which provides 10 or 20 nsec — a gain of almost 100 or 1000 times. "Most spin semiconductor work utilized GaAs or some other direct-gap semiconductor, because optical means were used to inject/detect the polarized electrons," LaBella said. "Polarized light is shined on it to create the spin population. Here, measurement becomes a crucial aspect of the work, because by measuring the polarization of the light coming out, it is possible tell something about the spin population."

2. View of spin transport metrology instrument under development at the College of Nanoscale Science and Engineering of the University at Albany. An STM tip is used to locally inject spin-polarized electrons into a spin-injection contact to study transport through the interface. (Source: University at Albany)

"We're trying to use spin in devices or interconnect structures between devices," LaBella said. "We've been looking at transport in silicon to make interconnect structures that won't suffer from the scaling effects that copper does." Because RC delay is caused by charge and resistance, in a spin current, there would ideally be no charge and, therefore, no RC time delay. And interconnects can be scaled, or spun, without delay. "Part of the research is how to make a spin interconnect using silicon, what the contact would be, how to read it out, and what data rate is possible. Much of it requires nanoscale lithography on silicon, combined with ferromagnetic metals or some type of wafer bonding, techniques that are rather foreign to a conventional fab line."

If a ferromagnetic metal is placed on a semiconductor, spin injection can be had (Fig. 2). "What often happens with silicon is that at the interface, you get a very thin silicide layer that is typically magnetically dead," La Bella said. "If magnetically dead, it decreases spin polarization. We've been studying the interface using a scanning tunneling microscope to look at the polarized electrons through that interface." Albany has developed special metrology techniques that look at the interface's effect on spin transport. That provides a means to probe candidate structures and understand why there are magnetically dead interfaces and how they decrease spin injection.

MEMS, optical integration

"We're at the state-of-the-art in integrating electronics with optical devices with MEMS," said John Gates, director of the nanofabrication research department at Bell Labs (Murray Hill, N.J.). "With world-class litho capabilities, 193 and 248 steppers, we can make moving parts on silicon of the same order of magnitude in size as the CMOS industry. We have moving elements, with dimensional parts — springs, interconnects — 150 nm to 300 nm wide, with ±20 nm alignment layer-to-layer requirements. We can make mechanical moving objects which are on electronics' basic unit cell." (Fig. 3)

3. In MEMS devices, such as those that have to do with imaging or use complex lenses, the density becomes much higher and cannot be dealt with using hybrid processes, therefore direct integration with the electronics is required. (Source: Bell Labs)

Bell Labs has developed the world's largest ceramic package, which is a package 40 layers thick with more than 5000 electrical connectors coming out the back. "The next step is putting electronics in the package," Gates said. "You hybridize optical and mechanical devices with electronics, and the next level is the interconnect between the IC and the MEMS or optical device in the package. This happens when you get down to 2 to 3 μm per electrical interconnect. Beyond that, you must be able to do vias going from the IC to the mechanical or optical device. That is where you must put materials on the CMOS wafer." For current standalone devices, such as a silicon wafer with some optical device, nanostrip, etc., which is then combined with some electronics, whether a sensor or a filter for optical applications, today's standard silicon IC processing tools are adequate to implement these optical/MEMS-based devices.

Metrology, reliability

Curt Richter, leader of the Nanoelectronic Device Metrology Project at the National Institute of Standards and Technology (NIST, Gaithersburg, Md.), believes that extending CMOS to its ultimate requires comprehensive measurements. "This will be the driver as new materials are investigated and brought in," he said. Also needed is research on how materials behave at the 1-3 nm scale. The resolution of many measurements must be improved specifically for analytical metrology capabilities, rather than process monitoring.

Strain is critical. It is easy to look at bulk strain, but now it must be done at the 1-3 nm scale. Nanoelectronic test structures that allow specific electrical and physical properties to be extracted must be developed. "You may not be able to look at a 2 nm object, but if it can be dropped into a test structure, its properties can be extracted using electrical, optical or some other kind of testing," Richter said.

Reliability is another matter. "To commercialize these technologies, we must understand failure and drift across all things, whether it is bringing in a new material into conventional CMOS or a completely different device structure," Richter said. "Reliability at nanoscale may be different than for bulk properties. Particularly for metals, it will be very different and a potential showstopper."

David Seiler, chief of the Semiconductor Electronics Division at NIST, agrees. "The reliability models used with new materials may not be up to the task, requiring a whole new set," he said. "It's not just the data on the mechanisms, but predictions of the actual chips' reliability. At ultimate thinness, we're dealing with nanoscale devices largely controlled by interfaces. Damage could occur more easily; electron traps be more readily produced." Thus, at the interface level, some sort of nanoscale probes and tools must be developed to look closely at interface properties. The ideal tool would reveal chemical properties, the physical placement of the various atoms, and the electrical properties of the device's connections.

"The Holy Grail is a tool that shows where every atom is in the structure, what kind of an atom it is in its chemical state," Richter said. "Devices are becoming so small one can no longer think of dopants as statistically uniform. But even if you found an individual dopant, you'd want to know whether it is activated or not."

Validated models for predictive device performance are needed. However, modeling is only one aspect. What is difficult is the experimental validation-making device prototypes and determining their performance, obtaining the physical characterization of those devices to feed back into a model of what the device looks like.

Seiler sees insufficient emphasis on reliability. "There is a need for a Center for Nanoelectronic Device Reliability that involves industry, academia and government in a more concentrated effort. NIST is beefing up its reliability investigative efforts and working on fundamentals as well as test."

Another problem is heat. At smaller scales, devices cannot operate at higher frequencies because they generate too much heat. A means to measure heat in devices, the various processes taking place, and somehow counteract heat generation is needed. "What temperature means at the nanometer scale is almost a philosophical matter," Richter said. "We need ways to effectively measure how hot things are to understand how to extract heat quickly and efficiently. The heat problem is a major driver in the search for alternate technologies."

Metrologies will be needed that measure traditional CMOS properties, but there will be other features that must be measured. For example, for MEMS, deflection must be measured with optical techniques or gas sensing, which may be incompatible with the CMOS core. Specialized metrologies and innovative technologies will enable different core technologies to communicate with each other.