SI CHINA     SI JAPAN
Login  |  Register          Free Newsletter Subscription
Subscribe
Email
Print
Reprint
Learn RSS

The Greatness of Verticalness

Peter Singer, Editor-in-Chief -- Semiconductor International, 8/1/2007

If you're reading this on our newly designed website, www.semiconductor.net, or in our digital edition, then you'll be able to easily click on the links that take you to the following articles and columns: “3-D Through-Silicon Vias Become a Reality” (June 2007); “Posturing and Positioning in 3-D ICs” (April 2007); “Deep Silicon Etching: An Enabler for 3-D Integration” (February 2007); and “EMC-3D Consortium Targets Cost-Effective TSV Interconnects” (February 2007). If not, don't worry — August's cover story, “Enabling 3-D Design,” provides a nice overview.

We have had a lot of coverage on 3-D integration so far this year, with more to come. Why? Is it really “the next best thing?”

I believe it is, and so do many others. “3-D integration will establish a new scaling path that will extend Moore's Law beyond its expected limits,” noted Steven Koester, Manager of Exploratory CMOS Technology at IBM (East Fishkill, N.Y.), in a recent webcast, “Ultra Thin Wafer Processing Solutions.”

3-D integration, where chips are thinned, stacked and interconnected, allows for “fusion” of various elements, including memory, logic, sensors and processors — and ultimately optoelectronics, biochips and MEMS — in a much smaller and thinner footprint. In memory stacks, it can provide a 1000× increase in speed and a 100× decrease in power consumption. Transfer rate between chips is in the terabyte/sec range, and there is the potential for an arbitrarily wide bus: designers could easily implement a 2000 line bus if they needed to. “It's not just stacking a bunch of memory,” noted Dick Post, CEO of NEXX Systems (Billerica, Mass.), in a recent company visit. It is about taking “old designs and reworking them,” although he admits that the designs tools needed to do so are not yet readily available (which is part of the reason why they partnered with Austin-based Cubic Wafer, a co-author of the cover story ). Koester said that 3-D integration will be applicable across a broad range of technologies and applications, from wireless communication to multicore microprocessors, which each have different technical requirements.

For the near future, the trend is to move from 2-D configuration to 3-D stacking (with wires, bumps and micro vias), and then move to 3-D ICs with through-silicon via (TSV) interconnects to reduce footprint, increase silicon efficiency, and have shorter interconnects. The industry is moving past the feasibility phase into the commercialization phase, “where economic realities will determine the technologies that are adopted,” as Jan Vardaman noted in “3-D Through-Silicon Vias Become a Reality ,” June's cover story.

Sitaram Arkalgud, Interconnect Division Director at Sematech (Austin, Texas), noted in the aforementioned webcast that 3-D has been around for quite some time as a packaging solution. But compared with more “conventional” solutions such as 3-D system-in-a-package (SiP) and 2-D system-on-a-chip (SoC), 3-D through-silicon via (TSV) had advantages in terms of performance, power, functionality and time to market. The deciding factor is going to be cost. “There is really where we are going to see whether through-silicon vias are going to make it or not. The cost is definitely lower than SoC, but it remains to be seen if it is close to SiP,” Arkalgud said. “We need proven cost-of-integration schemes. We need to have the manufacturing infrastructure in place.” The goal of the EMC-3D consortium, formed by Semitool, EV Group, Alcatel and XSiL , in addition to several institutes and material suppliers, is exactly that, with the ultimate goal of developing a 3-D process that is <$200/wafer.

I cannot conclude without again mentioning our new website, to which we have added a fair amount of depth or “verticalness.” We're working harder to bring you more of the news you need, led by News Editor David Lammers. In the “News from the Web” section, visitors will find news from industry news sources all around the web, powered by a search tool called Zibb. We have also added easy access to print articles, updated info channels, webcasts, reader polls and access to all of our newsletters. And what would a website be without blogs? Come check out mine, “Semi-Conscious ,” and post a comment. I double-dare you!

Email
Print
Reprint
Learn RSS

Talkback

Related Content

Related Content

 

By This Author

SPONSORED LINKS



 
Advertisement
SPONSORED LINKS

More Content

  • Blogs
  • Podcasts
  • Videos

Blogs

Videos

Advertisements





NEWSLETTERS
Plug in and get the latest SI news, trends and industry updates delivered free, directly to your inbox!

SI NewsBreak and Special Reports (Weekdays)
Wafer Processing Report (Monthly)
Lithography Report (Monthly)
Metrology Report (Monthly)
Clean Processing Report (Monthly)
Packaging Report (Twice Monthly)
©2008 Reed Business Information, a division of Reed Elsevier Inc. All rights reserved.
Use of this Web site is subject to its Terms of Use | Privacy Policy
Please visit these other Reed Business sites