NBTI: A Growing Threat to Device Reliability

The simultaneous demands for higher drive current at lower operating voltages has led to more serious concerns over negative bias temperature instability (NBTI), which significantly shifts threshold voltage and reduces drive current. There are also indications that NBTI worsens exponentially with thinning gate oxide, and Vt shifts on the order of 20-50 mV are serious for devices operating at 1.2 V or below. Therefore, work is underway to better understand and model NBTI mechanisms to ensure continued high reliability for 90 nm, 65 nm and future technology nodes.
 
In CMOS devices, the NBTI-induced threshold voltage shift will occur over a period of months or years, depending on the operating conditions of the device. For instance, the heat created when a microprocessor operates at 100°C creates stress that can shift the threshold voltage over time. NBTI is most problematic for high-performance or high-reliability devices, and analog/mixed-signal devices are more susceptible than digital devices. By identifying NBTI-threatened designs, IDMs, foundries and fabless companies can reduce costly chip respins and potentially millions of dollars invested in masks and low-yielding first silicon.

Bias temperature stress under constant voltage (DC) causes the generation of interface traps (N_IT) between the gate oxide and silicon substrate, which translate to device threshold voltage (V_t) shift and loss of drive current (I_on). The NBTI effect is more severe for PMOS FETs than NMOS FETs due to the presence of holes in the PMOS inversion layer that are known to interact with the oxide states.

Traditional DC stress testing leads to rapid degeneration of transistor parameters, V_t and I_D. However, when stress is periodically interrupted (AC stress), as it is during normal, frequency-dependent circuit operation, the degradation is at least partially recovered and lifetime is restored (Fig. 1 ). The interface traps generated during the on state of the transistors are partially annealed during their off state. For this reason, reliability engineers have come to realize that DC stress testing, where the transistor is always on, grossly underestimates device lifetime.

1. Under constant voltage stress (DC stress), threshold voltage shifts as a function of time. However, if the stress is periodically interrupted (AC stress), as it would during normal operating, the degradation may be significantly reduced, extending the projected lifetime. (Source: Agere Systems)

It is generally understood that NBTI degradation follows a reaction-diffusion process, and that the stress/relaxation cycles demonstrate a symmetry, which has been modeled. M.A. Alam of Agere Systems (Allentown, Pa.) recently found that the magnitude of NBTI degradation depends on frequency through a complex interplay of reaction- and diffusion-limited trap generation processes, and that the intrinsic symmetry of the stress and relaxation phases can account for the weak frequency dependence of the NBTI phenomena.¹ A group of researchers from Chartered Semiconductor Manufacturing Ltd. (Singapore) and the University of Texas (Austin) confirmed the difference in lifetime due to NBTI degradation under static vs. dynamic operation.² Because of a significant electrical passivation effect (recovery) of interface traps on pMOSFET operating in a CMOS inverter, they determined that the device lifetime under dynamic NBTI stress can be much longer than that projected under static NBTI stress.

In this study, the group also proposed a physical model for NBTI under dynamic operation that simulates a practical stress condition for a pMOSFET in a CMOS inverter. Through this modeling effort, the researchers were able to propose an interaction between the hydrogen and silicon dangling bonds, and they arrived at a method of determining a maximum operating voltage and projecting a lifetime of future scaled CMOS devices. They determined that the projected static lifetime for a pMOSFET device with 1.3 nm oxide, gate length of 0.12 µm and V_t of 30 mV, at 100°C, is approximately an order of magnitude less than the dynamic lifetime (one year vs. 10 years) due to the recovery effect, also known as electrical passivation. In the same study, they determined that the threshold voltage shift during both static and dynamic stressing does depend on gate oxide thickness for pMOSFETs with W/L=10/0.12 µm and gate thickness of 12-21 nm (Fig. 2). Indeed, the electrical passivation effect was larger for the thinner gate oxides. Electrical passivation also proceeded more rapidly when the applied electric field was increased.

2. The thinner the gate oxide, the greater the shift in threshold voltage. The effect is more severe for static NBTI than dynamic NBTI, as expected. (Source: Chartered Semiconductor, Univ. of Texas)

The NBTI mechanism is an electrochemical reaction that involves the electric field, holes, silicon-hydrogen bonds and temperature. During NBTI degradation, the hydrogen-silicon bonds at the Si/SiO₂ interface are broken, and the reaction is limited by the diffusion of hydrogen.

Interface traps are formed when hydrogen is released from a Si-H bond. The observed symmetry in ΔV_t, ΔN_IT and Δg_m (transconductance) implies that the complementary process, the passivation of interface traps caused by the absorption of hydrogen at the dangling bond site, may occur during electrical passivation.² The Chartered study proposed a process where Si-H interacts with a hole in the inversion layer or the source/ drain extension region during NBTI stress, the hole breaks the Si-H bond and creates an interface trap by releasing the hydrogen species (atom, molecule or ion) at the Si/SiO₂ interface. For ultrathin gate oxides, the ΔV_t is caused by the buildup of interface traps along the poly gate/oxide interface. When the gate bias polarity is reversed, the hydrogen species passivate the silicon dangling bonds and reduce interface trap density, N_IT.

DCIV testing can be used to monitor interface trap formation during stressing and passivation. When the measured bulk current in a gate-controlled bipolar junction transistor configuration is properly treated, the electron-hole recombination current, I_DCIV, which is proportional to the interface trap concentration, N_IT, can be successfully measured for devices with gate oxides down to 1.3 nm.²

A recent Intel report talks about the universal recovery behavior of negative bias temperature instability.³ The researchers reported that:

• NBTI recovery can reach 100% at 25°C.
• Recovery behavior is independent of stress voltage, stress time and temperature (<25°C).
• Recovered devices degrade at the same rate when restressed.

3. Schematic of the three steps of NBTI: degradation, driven by the breaking of hydrogen-passivated bonds; recovery; the repassivation of the bonds; and lock-in, where hydrogen is no longer available and full recovery becomes impossible. (Source: Intel)

The third observation indicates that recovery returns the device to its previous condition prior to re-stressing if given sufficient time. The researchers proposed a three-step model to describe the degradation and recovery processes (Fig. 3 ). The mechanisms include a voltage-accelerated degradation, bias- and degradation-independent recovery, and a temperature-driven lock-in step. They propose that it is the confluence of these three mechanisms that corrupt common field/temperature acceleration models for NBTI used today. In this study, oxide thicknesses of 4.5-15.0 nm were used, with stress and recovery temperatures from 125°C to -40°C and stress fields of 4-8 MV/cm. To avoid unintentional recovery during measurement, degradation was measured while stressing the drain at 50 mV and monitoring the linear drain current, I_dlin. ΔI_dlin is proportional to DV_t. Recovery percentage appeared to be independent of field. However, at higher temperatures, there appeared to be a permanent hardening of the oxide damage (lock-in), making full recovery impossible.³ In addition, devices that were allowed to fully recover and then were restressed, degraded at the same rate as during the initial degradation, refuting previous studies that indicated restressing leads to more rapid degradation.

Finally, the Intel researchers did not observe enhanced recovery with greater positive bias, which suggested that no charged species are formed; the hydrogen species responsible for recovery is likely neutral. They speculate that degradation is driven by the breaking of hydrogen-passivated bonds and that, during recovery, those bonds are repassivated. Lock-in occurs when hydrogen is no longer available for passivation due to loss through diffusion or through the formation of other stable species.

NBTI is commonly characterized by stressing discrete PMOS transistors at high temperature and electric field, and periodically interrupting the stress to measure the threshold voltage and drain current. One problem with this approach may be the capture of data during recovery. Therefore, using conventional modeling, the calculated activation energy will vary, which explains the myriad of values found in the literature.³ The Intel researchers suggest breaking out NBTI models for the different stages of degradation, recovery and lock-in steps and to measure degradation ~1 msec or 1 µsec after stress is removed to estimate true degradation that would occur with devices running at megahertz frequencies.

More on NBTI from Steven Goldsmith, Senior Manager, Corporate Communications, Agere Systems.