GaAs-on-Silicon, Finally!

Up until the late 1980s, GaAs-on-silicon was the focus of some intensive research at universities, wafer suppliers, MOCVD companies and research labs of many IC suppliers. The hope was that it would provide a platform whereby III-V optical devices and silicon digital technology could be combined on the same chip. But it really never proved viable, due to problems with the mismatch between the silicon and GaAs crystalline lattice, which caused a significant number of dislocation defects at the interface of the two materials, extending into the active area of the devices.

Suddenly, those problems appear to have been solved thanks to new research at Motorola (Schaumburg, Ill.). While working with strontium titanate, a material with a high dielectric constant (high k) that has applications as a gate dielectric and for DRAM capacitors, researchers noted that the lattice size of the material was such that it might make a good buffer material. "It turns out that strontium titanate has a lattice which is about 2% mismatched to silicon, but it's about halfway between silicon and gallium arsenide," said Jim Prendergast, vice president and director, Motorola Labs, Physical Sciences Research Lab. "The other interesting fact that we found out when we're growing this crystalline strontium titanate on silicon was that we're also getting an interface layer between the STO and the silicon, which was an amorphous silicon dioxide.

GaAs-on-silicon enables III-V optical devices, such as lasers and photodetectors, to be combined with silicon-based digital processors. (Source: Motorola)

"Amorphous silicon dioxide can act as a compliant layer. We believe that there is some level of compliance here. In fact, when we looked at the crystalline structure of the strontium titanate, it was completely relaxed. Based on that, one of our researchers, Dr. Jamal Ramdani, had the excellent idea of growing additional layers on top of the strontium titanate. His first try was to look at GaAs. He knew the lattice match would be pretty good to strontium titanate and, in fact, the second time he attempted to grow it, it was indeed successful." That was a little less than two years ago.

Researcher Ravi Droopad (left) is pictured with colleague Jamal Ramdani (right), who had the “excellent idea” of depositing GaAs on top of strontium titanate on top of silicon. (Source: Motorola)

"We've had just a crash program now here in Motorola Labs where we've been perfecting that technology, and we believe that we're at a point where we do have very good defect densities and are actually showing rf performance that's essentially equivalent to GaAs-on-GaAs," Prendergast added. Motorola Labs is now working on developing the optimum intermediate layer for indium phosphide and other materials.

Until now, the industry has been dependent on costly GaAs and InP wafers for optical and high-performance applications. Because of their brittle nature, no one has previously been able to create commercial GaAs wafers larger than 6 in. or InP wafers larger than 4 in. "We believe that GaAs-on-silicon starting material will be a lot less expensive than the equivalent GaAs-on-GaAs, even for the same wafer size," Prendergast said. "So a 6 in. GaAs-on-silicon would be significantly lower in production costs than an equivalent 6 in. GaAs-on-GaAs. You can imagine there would be even greater cost advantages in going to 8 in. or even 12 in." Motorola Labs created the world's first 8 in. GaAs-on-silicon wafer and worked with epitaxial wafer manufacturer IQE to create the world's first 12 in. GaAs-on-silicon wafers and a variety of other wafer sizes.

Motorola's announcement that it has successfully made GaAs transistors in a thin layer of GaAs grown on a silicon wafer could go down in history as a major turning point for the semiconductor industry, said Steve Cullen, director and principal analyst, semiconductor research, Cahners In-Stat Group .