Improving Copper Interconnect Reliability
Laura Peters, Senior Editor -- Semiconductor International, 7/1/2001
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• The determination of an EM threshold for copper interconnects with SiO2 dielectrics by IBM researchers (Hopewell Junction and Yorktown Heights, N.Y.).
• Stanford University's (Stanford, Calif.) introduction of a new thermal model to estimate joule heating in multilevel interconnects, taking into account the contribution of vias.
• A finding by Advanced Micro Devices (AMD, Sunnyvale, Calif.) researchers that light doping of copper to form CuSn, CuIn and CuZr alloys can reduce copper thin-film agglomeration and improve EM resistance.
The IBM group used standard electrical lifetime measurements and a simplified equation based on the Blech model to study the length-dependent EM behavior (the short-length effect) of copper interconnects stressed at current densities, j, of ~0.6-1.5 MA/cm2, at 295-400°C. Using a test structure of a single-damascene copper interconnect (0.245 µm (W), 0.31 µm (H)) with a tungsten stud at one end (V1) and a copper via at the other end (V2), the group tested interconnects of 30-100 µm long with an oxide/nitride cap.
Under stress, they found that all samples underwent an incubation period (no resistance change), then a sudden resistance jump (>10 W) due to EM voiding at the cathode (V2), and finally a steady resistance increase, due to excessive joule heating. After correlating the EM flux behavior with the Blech equation, the group found that the threshold length product, (jL)th, the value below which EM will not occur, became more prominent with decreasing temperature. The IBM group emphasizes the need for further characterization of the failure distribution and consideration of all the factors influencing (jL)th (aspect ratio, integration scheme, microstructure, barrier material, etc.), prior to design implementation.
Stanford researchers developed a model to help determine interconnect temperature rise (joule heating) as a result of combining low-k interconnects, with their lower thermal conductivity, with multi-level copper interconnects operating at high current density. The group's analytical expression contains a via correction factor, which quantifies the effect of via separation on the effective thermal conductivity of the intermetal dielectric. They assumed interconnect geometries from the ITRS 0.10 µm technology node, and a worst-case thermal conductivity of low-k polymer (0.3 W/mK). In excellent agreement with the 3-D finite element thermal simulation results, the model can be used to quickly predict temperature profiles in a device. Importantly, the temperature rise at each level is not as great when the model incorporates the vias' ability to spread heat. Therefore, joule heating associated with low-k dielectrics is not as severe as previously predicted.
The AMD Technology Development Group studied copper alloys with low in-film concentrations of Sn, In and Zr of 0.3-1.2 at% to determine the effect on copper seed layer integrity and EM resistance. The researchers used a two-metal-level EM test structure with M1 test lines terminated by a via and connected to M2 lines at each end. For the V1/M1 interface EM test, failure was forced in M1 using a wide M2 line and narrow M1 line (0.36 µm).
With all films, AMD researchers observed significant reduction of thin Cu film agglomeration on the TaN barrier, suggesting suppression of copper mobility along the Cu/barrier interface and reduced EM potential. The alloys raised the bulk resistivity of the films by 3.6, 1.1 and 18 µV-cm for CuSn, CuIn and CuZr, respectively (normalized to 0.3 at%). Upon annealing, resistance dropped by 30-50% (to levels comparable to pure copper) and the dopant redistributed into the bulk copper in theorderSn>In>Zr.
All three elements suppressed copper agglomeration, grain growth and Cu atom movement near the seed/barrier interface, resulting in better PVD seed integrity and EM lifetime improvement. The study showed that a 1000 Å CuSn film can improve EM lifetime by a factor of two.
For additional information on yield management, go to www.semiconductor.net/yield
