Fast Silicon Transistors Use Conventional Technology
Peter Singer, Editor-in-Chief -- Semiconductor International, 7/1/2001
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The 20 nm transistors are 30% smaller and 25% faster than the 30 nm gate length transistors announced by Intel in December, which also set world speed records.
Intel said the 20 nm transistors will be the basis of its 45 nm (0.045 µm) process generation, which the company plans to have in production around 2007. Of special significance is that these experimental transistors, while featuring capabilities that are generations beyond the most advanced technologies used in manufacturing today, were built using the same physical structure and materials used in today's chips.
In an interview with Semiconductor International, Rob Willoner, a market analyst for Intel's Technology and Manufacturing Group, said "One of the remarkable things about this is that it is a very traditional transistor architecture. We're really excited because we see that this is going to get into volume manufacturing much more easily than if we were using something much more radical." The only main change is that Intel plans to use a high-k gate dielectric by the time these transistors go into production. "Obviously, we've got a lot of work ahead of us to make these transistors as small as we're doing in the lab now, but the path is clear. We know what kinds of things we have to do to make this production-worthy," Willoner said.
| TEM cross section of Intel's 20 nm NMOS transistor. The polysilicon electrode appears to be somewhat squiggly, but that is a result of the cleaving method used to prepare the sample. In reality, the gates are more uniform. (Source: Intel) |
Many researchers have speculated that nanotechnology would replace silicon in the future, but Intel's research illustrates that silicon and nanotechnology are, in fact, complementary. "We still have not found a fundamental limit for making silicon transistors smaller," added Robert Chau, Intel Fellow and director of transistor research, Intel Logic Technology Development. "The pace of silicon development is accelerating, not decelerating."
In December, at the International Electron Devices Meeting (IEDM), Chau and fellow researchers presented details on the 30 nm transistor. Those transistors were fabricated using a standard two-mask phase-shift mask approach with 248 nm lithography. Retrograded wells, aggressively scaled source/drain and source/drain extensions, and thermal anneal temperatures below 1000°C were used. Although details were not released at press time, the 20 nm transistor employed similar technologies, scaled down even further.
For additional information on wafer processing, go to www.semiconductor.net/wafer
