Critical Technologies at SEMICON West
SI and EP&P Editors -- Semiconductor International, 7/1/2001
The biggest question at SEMICON West this year will likely not be a technical one, but rather an economic one: Have we reached the bottom of this downturn, and when will the upturn come? Of course, nobody really knows the answer to that, but we at Semiconductor International feel that the industry has reached the bottom, and the upturn could come as early as the end of this year or the beginning of 2002.
A harder question is, What application will lead us out of the downturn? PCs? Mobile phones? Video games? Some new application? Our feeling is that there won't be one killer app but a combination of several drivers, including telecommunications, consumer, computing, automotive, aerospace, medical, industrial, etc.
What has been good news for the semiconductor equipment and materials industry is that IC makers must come out of the downturn in a good competitive position. That means they've continued to develop and invest in new technologies that will give them a competitive edge. The three main technology drivers that have emerged over the past few years will still be the focus of this year's SEMICON West activities: 1) the move to smaller device geometries; 2) the implementation of new materials; and 3) the transition to 300 mm.
Wafer processing
| Model IC3D 845 and 875 DualBeam FIB/SEM tools are completely integrated 3-D metrology systems that support 0.13 µm device manufacturing. The systems combine in situ FIB milling and SEM imaging in a fully automated package. (Source: FEI Co., Hillsboro, Ore.) |
Even if transistors can be fabricated that switch at very high speeds, however, the challenge lies in maintaining that speed as signals move through on-chip interconnects and eventually off the chip. This is why interconnect time delays are so critical, and why new materials that lower the resistances and capacitances that signals encounter as they move through interconnects are so crucial. Copper and low-k processes are pressed in the current environment to deliver significant performance gains in cost-effective process modules. Electrochemical deposition processes are maturing, as are copper and low-k CMP processes. The change from SiN- to SiC-based etch stop layers and barrier films adds complexity to the already rapidly changing interconnect processes.
It appears that little of the learning for high-k dielectric materials for memories will translate to high-k gate dielectric needs, pushing the R&D of Zr and Hf oxide and silicate films along with their interaction with both polysilicon and metal gates.
The equipment and materials suppliers will continue to address these new areas, while also investing in mainstream computer integrated manufacturing and automation technologies that can carry over from 200 to 300 mm environments. The 300 mm wafer transition, driven strictly by economic concerns, is finally resulting in the confirmation of what equipment suppliers have said all along — that 300 mm will eventually allow a 30% overall cost reduction. Companies like TSMC are revealing the aggressive roadmaps for yield ramping and cost reduction needed to make 300 mm production a reality.
Advanced lithography
| The Model 410 semiautomatic flip-chip and laser diode bonder provides 6 2 µm placement accuracy. It is specifically designed for edge emitting laser diode applications. (Source: Semiconductor Equipment Corp., Moorpark, Calif.) |
Of course, the move down the NGL line is hardly a linear one. As one chipmaker decides to make the investment in production ArF scanners, for example, another is deciding to make use of mask sets with the most complex of resolution enhancement techniques (RETs), enabling continued use of 248 nm lithography systems.
Lithography system manufacturers will undoubtedly be striving to approach all such customers, offering a variety of systems that rely on different laser wavelengths, different numerical apertures, and support for such RETs as optical proximity correction and varying complexities of phase-shift masks. Likewise, expect to hear more from the mask makers, as their offerings become ever more critical and complex; and more from software developers that enable such mask design.
Various industry groups will also be addressing concerns with upcoming technologies, including difficulties with pellicles, optics materials (the quantity of reliable CaF2 could be a sticking point for 157 nm) and photoresists.
Inspection, measurement and test
Trends in metrology point to a higher level of integration in the production area, both for inspection and review tools. With 300 mm, fab automation becomes obligatory, which means inspection and review systems must operate as production tools.
With copper and the move to 0.13 µm, the industry recognizes that, in a high-volume production environment, modules are not as mature as aluminum's — CMP and electroplating being good examples. This is leading toward unprecedented — some say hyper — sampling rates to monitor all product.
Most yield problems do not result from the tool's inability to detect the trouble, but from slow reaction time. Hyper-sampling is viewed as a key strategy for processes such as copper CMP, which requires 100% inspection. Once robust in situ measurement techniques are implemented to track process progress, closed-loop control and APC become possible.
New materials and smaller geometries make this the era of the electrical defect. At 0.13 µm, copper voiding is a problem that can arise not from tool-induced defectivity, but from the interaction of processes with increasingly smaller windows. Since it will be necessary to inspect billions of vias for void detection to get feedback and necessary statistics, enhanced scanning voltage-contrast e-beam systems have become necessary tools.
A corollary to this is the development of more agile and intelligent inspection and review software, to process the vast amounts of data produced by new inspection and review systems. It is not enough just to find defects — enhanced ADC and defect-filtering capabilities are playing a crucial role in identifying yield killers.
Yield management
Yield management is simultaneously undergoing many changes — with the move to new materials, 300 mm wafers, smaller defects and new failure modes. Yield management is also challenged to ramp yields faster than ever before, requiring a coordination and focus moved from the unit level process module (i.e., PVD TiN) to layer-specific and interlayer phenomena. The rapid transition to 0.13 and 0.10 µm device generations is also dramatically increasing the volume of defects that need to be systematically characterized and eliminated.
Automated, through-the-production line yield management is becoming increasing essential — from design to fabrication to testing and packaged test. At the show, companies will be previewing new or enhanced software suites for more efficient defect data handling and feedback, with a strong focus on the lithography module.
The industry's move to new materials, particularly copper and low-k-based interconnects, is revealing a host of new failure mechanisms. The processes used to produce interconnects using copper and Ta/TaN barrier metals are becoming better understood, with ties between electromigration, feature dimensions and interface interactions coming to light. Even with this progress, however, companies are discussing the implementation of new barrier materials such as TaSiN and TiSiN and perhaps even carbide films as soon as the 90 nm device generation. Debate between the extension of PVD vs. CVD of barrier films continues, with PVD currently leading because of its better adhesion to copper seed and ECD films.
Assembly and packaging
While we still operate within a downturn environment caused by excess capacity, inventory and general global economic malaise, several packaging trends portend good news for the next upturn.
Some of the packaging trends the industry will debate at SEMICON West:
- Ball grid array (BGA), chip-scale packaging (CSP) and direct chip attach (DCA) are now maturing packaging technologies, with imminent growth phases.
- Flip chip is winning more converts as a high-density "patch" technology for many applications demanding greater performance in small spaces.
- Lead-free materials continue to generate great interest and consume R&D expenditures.
- Wireless and Bluetooth have cooled from white-hot to merely very hot new technologies.
More exotic new trends include system-on-a-chip, system-on-package and stacked die. All three technologies show closer alignment with front-end semiconductor processes, creating packaging opportunities in the fab. The 300 mm conversion promises advantages to wafer-level packaging (WLP) and further synergy with the front end.
Test and inspection procedures are trying desperately to avoid a "bottleneck" label and in the process have become huge growth areas.
Optoelectronics, the marriage of electrons and photons, has explosive growth potential. The requirement for speed at any cost drives this agenda, but the need for packaging automation threatens to sidetrack the effort.
