Characterize Gate-Level Transistor Performance with PICA
Ted Lundquist Schlumberger Probe Systems, San Jose Moyra McManus IBM Research, Yorktown Heights, N.Y. -- Semiconductor International, 7/1/2001
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PICA, invented by IBM researchers,2 changes the way probing is done. Before PICA, internal timing measurements involved putting something into the device to acquire a measurement. Mechanical microprobes, e-beams, laser beams, ion beams and even AFM-type probes put something in to get information out. PICA, on the other hand, collects data in parallel from individual transistors over a wide area. The phenomenon used by PICA technology is intrinsic to all CMOS transistors. Light is emitted from the channel of a CMOS transistor whenever current flows. Therefore, PICA allows the device itself to tell us what is happening.
Because metal layers, including the bonding pads, restrict light emission (unless special provision is made to provide access) and because silicon is somewhat transparent in the infrared (IR), PICA becomes a natural candidate for back-side diagnostics. Further, as process technologies shrink to 0.13 µm and beyond and change to include materials such as silicon on insulator (SOI) and low-k dielectrics, back-side e-beam and laser voltage probing may become too invasive. PICA's ability to collect timing information from the back side of ICs is a timely addition to the IC diagnostic tool box.
As in all probing techniques, a tester outputs the required test pattern to the DUT as well as acquires time-resolved voltage data from the I/Os during the probing session, while the prober acquires time-resolved (switching) data from the internal nodes of the IC. A repetitive looping of the failure-inducing test pattern achieves a high signal-to-noise ratio (SNR).
Data accessible with PICA
A PICA database contains timing information from all transistors within the field of view (160 µm diameter at 100×) over the entire length of the test loop. This eliminates the need to know precisely where or when to probe, as in the case of single-point probing. The description of the data is therefore simplified and readily available for parallel analysis. With PICA movies, IC engineers/designers can "see" what happens inside their IC as it operates. This enables debugging to the transistor level, thereby tracking down the origin of failures and design errors and drastically reducing debug time — leading to faster development cycles.
PICA also allows IC engineers/ designers to "probe" flip-chip ICs as well as front-side ICs if mounted in tabBGA, EBGA or other cavity-down packages. When front-side ICs are designed so light emitted from the transistor channel is not blocked by metallizations, those ICs can be front-side analyzed with PICA. In fact, any front-side design, where the transistor is not blocked by metallization, can be "probed." Other measurements that PICA is capable of determining:
•Timing/switching analysis — Failures that cause faulty operation only at or near maximum operating speed are diagnosed by acquiring emission from a pre-selected field of view and observing circuit element delays to identify timing conflicts. Results often reveal signal path length differences, which are the root cause of the fault.3 A PICA movie utilizes the inherent efficiency of the human brain to interpret visual patterns. Comparing a PICA movie of a "golden device" with a movie of a problem device, or of two movies of the same device running at different speeds, is an efficient way to get to the heart of a complicated timing problem.
•IDDq analysis — IDDq failures result from several causes (bridge faults, shorts through thin oxides, leaking transistors, etc.). Characterization of IDDq failures cannot only validate the effectiveness of the IDDq test, but can also improve its coverage as well as overall yield. For example, a circuit can pass all logic tests but have high IDDq; PICA cannot only locate the short but also determine the delay caused by the defect.
•Detailed delay characteristics — The ±15 psec timing accuracy achieved by PICA allows variations in interconnect lengths and loading to be measured.4,5
•Clock skew analysis — Clock distribution analysis can be made to determine the offset between the reference clock and various receivers on an IC. Further skew among fanout buffers can be determined.6,7
Collecting data
| 1. With V dd applied to the n-MOS gate, electrons flow in the channel, emitting photons. With V dd removed from the p-MOS gate, holes flow in the channel, emitting fewer photons overall due to their lower mobility. |
To maximize detection through the silicon substrate, three preparation steps are required — thinning, polishing and adding an antireflection coating (ARC) — steps identical to DUT preparation for an LVP tool.8 A detector with single-photon sensitivity is used to capture the faint IR emission (1-1.4 µm) from each transistor. Further, because the photon detection probability for the time-resolved imaging detector is small (~1 detected photon per 108 transistor switches), transistors are switched on and off repeatedly. Random events (dark counts)within the detector determine noise, so test pattern cycling increases SNR in the "waveform." The measurement is halted once sufficient SNR is achieved, and the acquired data is available for immediate examination or is archived for off-line analysis.
Because PICA is essentially passive, the PICA operator does not have to attend data interpretation sessions and thus the data can be analyzed remotely. Data collected is post-processed to show device operation. The raw emission data becomes the "movie."9 Integration over time of collected data creates an emission micrograph that can be overlaid
onto its corresponding LSM image to show the location of all transistors switching during that particular test sequence (Fig. 2).
Selection of a single emission point in x, y of the collected data and plotting its emission intensity as a function of time yields an optical waveform,2 which to some measure is a derivative of the traditional voltage waveform. Figure 3 shows two such "optical" waveforms plotted together.
The x, y position registration of the PICA emission data to the LSM image enables registration to the CAD layout and then correlation to the schematic. This schematic correlation provides a means for comparison and ultimately input to circuit simulation. Logic evolution and specific delays can be deduced from the waveform information. A timing error is determined by comparing measured switching times with simulated switching times. By comparing measured switching activity in a particular test pattern to the predicted switching activity, a stuck at high/low can be determined. The PICA database can be "mined" immediately or transmitted anywhere in the world for off-line analysis.
Case study: IBM S/390 G5 microprocessor4
| 3. PICA data displayed as time scan of n-MOS transistor in inverters #1 and #9 as in Figure 2. The FWHM of the peaks is <100 psec. The delay between inverters #1 and #9 switching is measured as 508 psec, giving an average inverter stage delay of 63.5 psec. |
One I/O test, running at specification frequency, measured a wrong value on a particular I/O pin. Figure 4 (top) shows a simplified schematic of the I/O circuit and the failing condition X. X was slow to switch from 1 to 0 when DI was switched from 1 to 0 and A was kept at 0. The tester-based approach could not identify whether the failure was transistor T25, gate 1, gate 3 or was due to an interconnect short or open. PICA data gathered included a number of I/O circuits. Figure 4 (middle) shows a time-integrated emission image from the area of T25 (circled) as well as the optical waveform (emission vs. time) from T25. Figure 4 (bottom) provides comparison to a "good" transistor (circled). The "optical" waveform for gate 1 and for gate 3 from both the faulty and the good circuits were equivalent. This information localized the defect to the gate of T25 or to the interconnect from gate 1 to T25. Both of these possible defects were sequentially put into the fault simulator program for qualitative comparison with the actual emission of Figure 4.
| 4. Schematic of I/O circuit (top), emission image and time scan comparing bright defective (middle) and good (bottom) I/O gates from the same G5 microprocessor. |
Case study: IBM S/390 G6 microprocessor
For the debug of the IBM S/390 G6 microprocessor,10,11 PICA was used to measure internal timings in the region with issues. Tester-based analysis, using programmable random access memory built-in self-test (RAMBIST), had identified the L1 cache memory control circuit as the region demonstrating cycle problems. Emission measurements under passing/slow (2.25 nsec cycle) conditions and under failing/fast (1.5 nsec cycle) conditions showed markedly different emission intensity in the region of issue, implicating the cache memory control circuit in the failure. To allow comparison by direct image subtraction, the measurement time for the passing case was 50% longer (Fig. 5).
| 5. Photon emission difference image (left) created from device passing image (center), subtracted from scaled failing image (right), all overlaid on the corresponding microscope image. |
Addressing limitations
Looking at the future technologies on the SIA roadmap,12 one can see that traditional test and debug technologies are not compatible with the future (0.13 µm and beyond, SOI, etc.), but PICA is. PICA is especially suited for SOI circuits for three reasons: 1) SOI chips can be more sensitive to invasive techniques; 2) SOI chips have undoped silicon substrates that are almost transparent for IR photons with wavelengths of 1.1 µm and longer; and 3) As needed, the silicon substrate can readily be completely etched away to leave only the oxide insulating layer between air and the diffusions.
Hardware development should keep pace with the SIA roadmap in the specific areas of time and spatial resolution — detector sensitivities can be improved.13 The present bandwidth of the IDS PICA is 2.1 GHz, but new detector development can push this much further. Conventional diffraction-limited IR optics can provide transistor resolution to 0.70 µm transistor separations.
By 2012 the SIA roadmap has transistor spacings falling to 0.55 µm — below the 0.70 µm of conventional optics. But unconventional light optics such as immersion lenses could extend PICA's direct usefulness further.
Unsurpassed time-resolved imaging by detecting IR photons results in volumes of data. The full benefit of all this data requires the computing power of modern computer systems. The data are readily archived for reference by designers and debug engineers as well as interpretation by process engineers. Moving forward, this data handling will become more sophisticated.
Future IC designs may include specific features to enable the optimal use of PICA. These designs for diagnostics might specify access to PICA emissions through multi-level metallizations for front-side packages, or specify special PICA emitter designs for increased emission at critical nodes for back-side packages.
Ted Lundquist is market manager for the Probe Systems Group, Schlumberger Semiconductor Solutions, and has more than 25 years of experience in ion optics and instrumentation. Before joining Schlumberger in 1994, he was at Gatan Inc. for 15 years, serving as development manager for ion optics and developing ion beam systems including FIB (focused ion beam) systems. Previously he was at NASA developing beam techniques to calibrate mass spectrometers. He has a B.S. from the Massachusetts Institute of Technology, an M.S. from the University of Massachusetts, and a Ph.D. from the University of Maryland.Moyra K. McManus is the Picosecond Imaging Circuit Analysis (PICA) manager for IBM Research, where she has been responsible for developing PICA methodologies for the last three years. She previously held a post-doctoral position at Brookhaven National Laboratories. She has a B.A. and an M.S. from the University of Montreal, and a Ph.D. in solid-state physics from Simon Fraser University.
REFERENCES
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- D. Knebel, et al, "Diagnosis and Characterization of Timing-Related Defects by Time-Dependent Light Emission," Proc. of IEEE Intern. Test Conf., 1998, p. 733.
- J.A. Kash, J.C. Tsang, "Hot Luminescence from CMOS Circuits: A Picosecond Probe of Internal Timing," Phys. Stat. Sol.(b) 204, 1997, p. 507.
- S. Polonsky, "Non-Invasive Timing of IBM G6 Microprocessor L1 Cache Using Backside Time-Resolved Hot Electron Luminescence," Digest of the IEEE Intern. Solid State Circuits Conf., 2000.
- P.N. Sanda, et al, "Picosecond Imaging Circuit Analysis of the POWER3 Clock Distribution," Digest of the IEEE Intern. Solid State Circuits Conf., 1999, p. 372.
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- K. Wilsher, W.K. Lo, "Practical Optical Waveform Probing of Flip-Chip CMOS Devices," Proc. of IEEE Intern. Test Conf., 1999, p. 932.
- www.research.ibm.com/topics/popups/serious/chip/html/pica.html.
- W. Huott, et al, "The Attack of the Holey Shmoos: A Case Study of Advanced DFD and Picosecond Imaging Circuit Analysis (PICA)," Proc. of IEEE Intern. Test Conf., 1999, p. 883.
- M. McManus, et al, "Picosecond Imaging Circuit Analysis of the IBM G6 Microprocessor Cache," Proc. of the 25th ISTFA, 1999, p. 35.
- International Technology Roadmap for Semiconductors: Interconnects, Assembly and Packaging, 1999.
- D.L. Barton, "Infrared Light Emission from Semiconductor Devices," Proceedings of the 22nd ISTFA, 1996, p. 9.
