Identifying the Most Promising High-k Gate Dielectrics

Robert M. Wallace University of North Texas, Denton, Texas Glen D. Wilk Agere Systems, Murray Hill, N.J. -- Semiconductor International, 7/1/2001

	At a Glance
The industry is pursuing many paths to identify the best alternative high-k dielectric or dielectric stack. Certain materials hold great promise for this application. In Part 2 of this two-part series, we detail how pseudo-binary films such as metal silicates seem to exhibit the best prospects for interface control and thermal stability in contact with silicon, while also demonstrating compatibility with poly-Si or metal gate electrodes.

CMOS transistor scaling is rapidly reaching performance limits with traditional materials. As we discussed in the first part of this series (see "Exploring the Limits of Gate Dielectric Scaling, " Semiconductor International, June 2001), beyond a practical limit of ~12 Å thickness, new materials will be required to extend device performance, perhaps as soon as the 100 nm generation. New high-k gate dielectric materials systems must demonstrate key properties,¹ including high permittivity (or dielectric constant, k), barrier height to prevent tunneling, stability in direct contact with silicon, good interface quality and film morphology. The high-k dielectric must also be compatible with the gate material, semiconductor processing temperatures and operating conditions, and must produce MOSFETs with uncompromised reliability.

Here we discuss the potential that a variety of high-k materials hold in each of these key areas. Upon examining the research to date on oxide and silicate materials based on titanium, tantalum, strontium and other metals, we recommend further testing of pseudo-binary oxides based on zirconium and hafnium metals. These compounds provide good interface quality with silicon and appear to be compatible with both poly-Si and future metal gate electrodes.

Permittivity and barrier height

Selecting a gate dielectric with a higher permittivity than that of SiO₂ is clearly essential. Permittivities have been measured on bulk samples for many simple oxides and, in some cases, even on thin films. For more complex materials, the dielectric constants may not be well known.

The required permittivity must also be balanced against barrier height to limit tunneling. For electrons traveling from the silicon substrate to the gate, this barrier is the conduction band offset, D E_C. A gate dielectric must have a sufficient D E_C value to poly-Si, and to other gate materials, in order to obtain low off-state currents (leakage). If the experimental D E_C is <1.0 eV, it will likely preclude the oxide's use in gate dielectric applications because thermal emission or tunneling would lead to unacceptably high leakage currents. Reported values of D E_C for most dielectric-Si systems are scarce in the literature, but recent calculations indicate that many of the metal oxide and complex oxide materials, such as Ta₂O₅ and SrTiO₃, should have a D E_C of <0.5 eV on Si.² Since many potential gate dielectrics do not have reported D E_C values, the closest, most readily attainable indicator of band offset is the bandgap (E_G) of the dielectric. A large E_G generally corresponds to a large D E_C, but the band structure for some materials also has a large valence band offset, D E_V, which constitutes most of the dielectric's bandgap.

1. As shown in this hypothetical transistor gate stack, a high-k material can be physically thicker yet provide an oxide-equivalent thickness that is electrically thinner (t eq =10 Å for both) than would be possible using oxynitride dielectrics.

Among the several materials that have been investigated as gate dielectrics (Table), the dielectric constant generally exhibits an inverse relationship to the bandgap. In the cases of Ta₂O₅ and TiO₂, both materials have small D E_C values that correlate, in part, with high leakage currents. However, La₂O₃, HfO₂ and ZrO₂ offer relatively high values for both k and E_G.

Because of this relationship between bandgap and permittivity, a dielectric withk>25 is not necessarily required to replace SiO₂. The more relevant consideration is whether the desired device performance and reliability can be obtained without producing unacceptable leakage. Identifying a dielectric that provides even a moderate increase in k, but that also produces a sufficiently large tunneling barrier and high-quality interface to Si, is key. For example, if a single dielectric layer could be used, even a material with a k~12-20 could result in a physical dielectric thickness of 35-50 Å, obtaining an oxide equivalent thickness (t_eq) value that meets the requirements for 0.1 µm CMOS and beyond.

Relevant Properties of High-k Dielectric Candidates
Material	Dielectric constant, k	Bandgap, EG (eV)	Conduction band offset to Si, D EC (eV)	Crystal structure
SiO2	3.9	8.9	3.2	Amorphous
Si3N4	7	5.1	2	Amorphous
Al2O3	9	8.7	2.8*	Amorphous
Y2O3	15	5.6	2.3*	Cubic
La2O3	30	4.3	2.3*	Hexagonal, cubic
Ta2O5	26	4.5	1-1.5	Orthorhombic
TiO2	80	3.5	1.2	Tetragonal (rutile, anatase)
HfO2	25	5.7	1.5*	Monoclinic, tetragonal, cubic
ZrO2	25	7.8	1.4*	Monoclinic, tetragonal, cubic
*Calculated by Robertson2

Thermodynamic stability on silicon

For all thin gate dielectrics, the interface with silicon plays a key role, and in most cases is the dominant factor in determining overall electrical properties. Most of the high-k metal oxide systems investigated so far have unstable interfaces with Si — typically reacting with Si to form an undesirable interfacial layer, which then requires a reaction barrier.

Of course, an interfacial layer of SiO₂ or another low-permittivity material will ultimately limit the highest possible gate stack capacitance or, equivalently, the lowest achievable t_eq value (as explained in Part 1 of this series), according to:

When the structure contains several dielectrics in series, the lowest capacitance layer dominates the overall capacitance and also sets a limit on the minimum achievable t_eq value. The capacitance of two dielectrics in series is given by:

For instance, a dielectric stack structure with an SiO₂ bottom layer and a high-k alternative gate dielectric top layer simplifies Eq. 3 (assuming equal areas) to:

Since the minimum achievable equivalent oxide thickness (defined as t_eq) will never be less than that of the lower-k layer, a bilayer approach necessarily compromises the performance of the high-k dielectric film. Figure 1 illustrates two idealized gate stack structures, each comprised of layers with very different k values, and both of which result in a t_eq=10 Å.

Interface behavior

2. Ternary phase diagrams show the oxide and silicate compounds made with Ta, Ti and Zr. Tie lines between compounds indicate stable compounds formed when in contact at T=900degC and below. Unlike Ta- and Ti-based films, Zr compounds are stable in direct cont act with silicon. The blue shaded area highlights a large phase field of stable compositions of Zr-Si-O, implying that the level of Zr incorporated into the film could be gradually increased from one technology node to the next, or even within the film, allowing Si interface control.

An analysis of the free energies governing the relevant chemical reactions for ternary systems formed between tantalum (Ta), titanium (Ti) and zirconium (Zr) and silicon and oxygen gives the phase diagrams shown in Figure 2. In the Ta-Si-O and Ti-Si-O ternary systems, as shown in Figure 2a and Figure 2b, Ta₂O₅ and TiO₂ (or mixtures with Si), respectively, are not stable to SiO₂ formation when placed next to silicon.^3,4 Rather, Ta₂O₅ and TiO₂ on silicon will tend to phase separate into SiO₂ and metal oxide (M_xO_y, M=metal) and possibly silicide (M_xSi_y) phases. This instability to SiO₂ formation has been observed experimentally for both of these metal oxides,^5,6 which leads to the necessity for an additional interfacial layer.

In contrast to the Ta and Ti systems, the tie lines in the phase diagram for the Zr-Si-O system,⁷ indicate that the metal oxide ZrO₂ and the compound silicate ZrSiO₄ are both stable in direct contact with Si up to high temperatures. The blue shaded area in Figure 2c denotes a large phase field of (ZrO₂)_x(SiO₂)_1-x compositions, called "pseudo-binary oxides," which are also expected to be stable on Si up to high temperatures.⁸ The existence of this large phase field of stable compositions implies that the level of Zr incorporated into the silicate film could be gradually increased from one technology node to the next, or even within the film. This behavior is expected to be the same for the Hf-Si-O system based on coordination chemistry arguments.

This fundamental difference from the Ta and Ti systems is extremely important because it suggests that there is potential to control the dielectric-Si interface. Although it is certainly the case that all deposition techniques of interest are done under non-equilibrium conditions, it is unlikely that a desirable, metastable phase, such as amorphous Ta₂O₅, will be maintained throughout all the thermal cycling required for CMOS processing. Even in the case of process modifications such as a replacement gate flow,⁹ subsequent thermal cycling is sufficient to result in poor electrical properties. It is therefore important to select a materials system in which the desired final state is a stable one.

Such pseudo-binary oxides may allow for control of the Si interface, and may solve a key problem for the high-k gate dielectric material approaches. Of course, the k values of silicates are substantially lower than those of pure HfO₂ and ZrO₂, but this tradeoff for interfacial control is acceptable as long as the resulting leakage currents are low enough. Also under investigation are "silicate" materials that incorporate lanthanum (La) and yttrium^10,11 (Y), as well as analogous "aluminate" materials.¹²

Interface quality

It is difficult to imagine any material creating a better interface than that of SiO₂, since typical production SiO₂ gate dielectrics have a low midgap interface state density, D_it, of ~2 × 10¹⁰ states/cm². Most high-k materials reported show D_it values of ~10¹¹-10¹² states/cm², while also exhibiting substantial flatband voltage shifts (DV_FB>300 mV), possibly caused by fixed charge densities of >10¹²/cm² at the interface.

To maintain a high-quality interface and channel mobility, we expect it to be important to have no metal oxide or silicide phases present at or near the interface to the channel. However, because of high oxygen diffusivities, several simple oxides readily form SiO₂ or SiO₂-containing interface layers, severely compromising the capacitance gain from high-k layers in the gate stack. Another issue of concern results from exposure to forming gas (typically 90% N₂:10% H₂), the ambient commonly used in transistor annealing. Since many high-k dielectrics are reduced in the presence of H₂, it must be determined if the exposure will effectively passivate interfacial traps with hydrogen.

The ideal gate dielectric stack may well turn out to have an interface comprised of several atomic layers of Si-O (and possibly N), containing a pseudo-binary oxide. This oxide layer could preserve the critical, high-quality nature of the SiO₂ interface while providing a higher k value. Then a different, higher-k material could be used on top of this interfacial layer.

Film morphology

Most advanced gate dielectrics studied to date have focused on either polycrystalline or single-crystal films. Yet it is desirable to select a material that remains in a glassy phase (amorphous) throughout processing. As shown in the Table, nearly all bulk metal oxides of interest, with the exception of Al₂O₃, have a preferred crystalline phase. However, depending on composition and thermal processing, there will be some suppression of crystallization for very thin films.

Polycrystalline gate dielectrics are problematic because grain boundaries serve as high-leakage paths, likely leading to the need for an amorphous interfacial layer to reduce leakage current. In addition, grain size and orientation changes throughout a polycrystalline film can cause significant variations in k within the gate area, leading to irreproducible properties.

In principle, grain boundaries can be avoided by growing single-crystal oxides by molecular beam epitaxy (MBE) methods.¹³ MBE can provide a good interface, but the requirement for sub-monolayer deposition control may dictate a low-throughput MBE approach.

Given concerns regarding polycrystalline and single-crystal films, it appears that an amorphous film remains the ideal structure for the CMOS gate dielectric. The pseudo-binary materials systems, such as Hf-Si-O, have fewer stable ternary crystalline compounds (e.g., HfSiO₄). As a result, a range of compositions can be obtained that will remain amorphous and stable on Si up to high temperatures.

Gate compatibility

A significant integration issue for any advanced gate dielectric is compatibility with Si-based as well as metal gates. Of course, Si-based gates (including Si_1-xGe_x gates for achieving higher boron activation levels^14,15) are desirable because dopant implant conditions can be tuned to create the desired threshold voltage for both n-MOS and p-MOS transistors. Also, the process integration schemes are well established in industry. Unfortunately, nearly all of the high-k gate dielectrics investigated to this point require metal gates. TiN and platinum (Pt) metal gates have been used with most of the high-k gate dielectrics mentioned above to prevent reaction at the gate interface.

Even initial attempts to use poly-Si gates with ZrO₂ have been unsuccessful,¹⁶ although more recent work has shown improved poly-Si stability on HfO₂.¹⁷ However, a pseudo-binary system, such as a silicate in contact with a poly-Si electrode, has more inherent stability because the dielectric already contains a significant amount of silicon.⁸

The dielectric Al₂O₃ appears to be stable with respect to reaction with the poly-Si gates throughout typical CMOS processing.^18-20 However, both boron and phosphorous dopant diffusion have been observed with Al₂O₃ gate dielectrics, which cause significant, undesired shifts of V_FB and V_t values.^18,20 The formation of an Si-Al-O interfacial layer has recently been noted for Al₂O₃ films on Si after O₂ anneal at T~700°C as well.²¹

One key advantage to using metal gates is the elimination of dopant depletion effects and sheet resistance constraints. Current roadmap predictions indicate that poly-Si gate technology will likely be phased out beyond the 70 nm node, after which a metal gate substitute will be required.²²

3. The threshold voltages for n-MOS and p-MOS devices using midgap metal gates (a) and dual metal gates (b). The midgap single metal approach unfortunately results in unacceptably large threshold voltages (~0.5 V), but the dual metal approach could produce V T in the range of 0.2 V, for instance, using Pt (p-MOS) and Al (n-MOS). However, processing and interface requirements rule out the use of Pt and Al.

By using metal gates in a replacement gate process, one can lower the thermal budget by eliminating the dopant activation annealing step of the poly-Si electrode. Researchers are pursuing two basic approaches — using a single metal electrode material or two metals, optimized for the p-MOS and n-MOS devices. Figure 3 shows the energy diagrams associated with these two approaches.

In choosing a single metal electrode, it is important to select a metal with a work function (F _M) value that places its Fermi level at the midgap of the Si substrate. Such is the case with TiN (Fig. 3a). A major drawback to the midgap metal approach is silicon's fixed bandgap of 1.1 eV, making the threshold voltage for any midgap metal on Si in the range of ~0.5 V for both n-MOS and p-MOS. Since voltage supplies are expected to be ~1.0 V for 0.10 µm CMOS technology, a V_t~0.5 V is much too large because it would be difficult to turn on the device. Some researchers have also predicted that midgap work functions will not provide a performance improvement that justifies the added process complexity.²³

A second approach uses two separate metals (Fig. 3b). In the ideal case shown, the F _M value of Al could achieve V_t~0.2 V for n-MOS, while the higher F _M value of Pt could achieve V_t~0.2 V for p-MOS.

In practice, Al is not a feasible electrode metal because it will reduce nearly any oxide gate dielectric to form an Al₂O₃-containing interface layer. Other metals with relatively low work functions, such as Ta and TaN, however, are feasible gate metals for n-MOS. Similarly for p-MOS, Pt (and other noble metals) is not a practical choice for the gate electrode since it is not easily processed, does not adhere well to most dielectrics and is a costly material.

As an alternative, conducting metal oxides such as iridium oxide (IrO₂) and ruthenium oxide (RuO₂), both studied and used in DRAM applications, can provide high work function values in addition to affording the use of standard etching and processing techniques. Recently, RuO₂ has been examined as a potential gate electrode for p-MOS devices.²⁴ The prospect of using a single metal, such as Mo, which appears to be modified by N⁺ implantation to result in a "tunable" FM similar to poly-Si, has also recently been presented.²⁵ The pseudo-binary oxides are predicted to be stable next to Si-based gates as well as metal gates. A key issue for gate electrode materials research involves controlling the gate electrode work function (Fermi level) throughout CMOS processing.

Process compatibility

A crucial factor in determining high-k dielectric final film quality and properties is the choice of deposition process. It must be compatible with current or expected CMOS processes, cost and throughput metrics. Since all of the feasible, available deposition techniques occur under non-equilibrium conditions, it is certainly possible to obtain unique properties. It is therefore important to consider the various manufacturable methods such as physical vapor deposition (PVD, e.g. sputtering and evaporation), chemical vapor deposition (CVD) and atomic layer deposition (ALD).

PVD methods have provided a convenient means to evaluate alternate dielectric materials systems. However, PVD's inherent surface damage results in unwanted interfacial states. Additionally, device morphology inherent to submicron scaling generally rules out such line-of-sight PVD approaches. For these reasons, CVD methods have been preferred.

The reaction kinetics associated with thin-film CVD requires control of interfacial layer formation. The precursor employed in the process must also be tailored to avoid film impurities and permit useful final compositions in the dielectric film. Indeed, a graded composition for dielectric films may prove crucial to controlling interface state formation to a level comparable to SiO₂. The recent application of ALD methods for depositing Al₂O₃, ZrO₂ and HfO₂ appears to provide much promise, since self-limiting chemistries are employed to control film formation in a layer-by-layer fashion.¹ Researchers should carefully consider the pre-gate dielectric surface preparation method and resultant chemistry. A compatible etching process is also essential.

Reliability

The determination of whether or not a high-k dielectric satisfies the strict reliability criteria requires a well-characterized materials system — a prospect not yet available for the alternate dielectric materials considered here. The nuances of the dependence of voltage acceleration extrapolation on dielectric thickness and the improvement of reliability projection arising from oxide thickness uniformity have only recently become understood, despite decades of research on SiO₂. New high-k materials are sure to exhibit subtleties in device reliability that differ from those of SiO₂.

Nevertheless, preliminary projections appear to be encouraging for Al₂O₃¹⁹ and HfO₂ films.^26,27 Similar preliminary measurements of ZrO₂ films appear to be somewhat mixed — both very promising¹⁵ and less encouraging²⁸ results have been reported. Results of reliability investigations for pseudo-binary alloys are not yet published. It is clear, however, that the determination of the preferred dielectric constituent composition has yet to be completed, therefore making even initial reliability extrapolations problematic.

Conclusions

We presented the key materials considerations for alternate gate dielectrics and their corresponding gate electrodes. Though several promising candidates have been identified, the industry has yet to select a high-k dielectric material that satisfies all the considerations of high permittivity, adequate barrier height, reliability, compatibility with silicon and other gate materials, as well as CMOS process compatibility.

The pseudo-binary materials systems such as silicates offer significant potential toward the ultimate goal of integrating a novel gate dielectric into future CMOS technology nodes. Key advantages to these materials include stability in direct contact with silicon and possible maintenance of an amorphous structure throughout CMOS processing.

Researchers have yet to determine whether pseudo-binary materials are best suited as an interfacial layer to Si with a higher-k layer on top, or are able to comprise the entire gate dielectric stack.

Robert M. Wallace is a professor of materials science and director of the new Laboratory for Electronic Devices and Materials at the University of North Texas. He formerly worked for Texas Instruments, most recently leading a research team in TI's Central Research Laboratories that focused on advanced device concepts and material integration issues. He has a Ph.D. in physics from the University of Pittsburgh.
e-mail: rwallace@unt.edu

Glen Wilk is a member of the technical staff in the Electronic Device Research Laboratory at Agere Systems (formerly Lucent Technologies' Bell Laboratories). He specializes in advanced CMOS device integration as well as materials for high-speed and optoelectronic devices. He previously worked at TI's Central Research Labs. He has a Ph.D. in applied physics from Harvard University.
e-mail: gwilk@agere.com

---

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ACKNOWLEDGMENTS

Robert Wallace appreciates the support of the Texas Advanced Technology Program and the Semiconductor Research Corp. for help in the preparation of this series of articles.

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