Surface Preparation for Advanced Interconnect Schemes

Graham Hills Surface Integrity Group Novellus Systems Inc., San Jose -- Semiconductor International, 7/1/2001

At a Glance
A look at the challenging requirements for residue removal in dual-damascene schemes using a low-k dielectric and copper.

The continuous forces to increase functionality, produce better yields and lower the cost of devices drive the semiconductor equipment industry. The need for improved processes and equipment is not just manifest in applications such as chemical vapor deposition (CVD), physical vapor deposition (PVD), etch and lithography — generally considered more critical — but also in the areas of photoresist removal and surface cleaning.

The need for improved capability in photoresist removal and surface cleaning has become especially important for back end of line (BEOL) process steps where many new materials and technologies are being introduced. In particular, the technology trends in advanced interconnect structures at 0.13 µm and below require low-k dielectric materials and copper interconnects in dual-damascene structures.

A possible dual-damascene scheme appropriate for an organo-silica glass (OSG) — or carbon-doped glass — is shown in Figure 1. There are three places in the sequence for the dual-damascene unit module, indicated (a), (b) and (c), where cleans are required — twice after etch steps (a) and (b) and once after the copper CMP step (c). In this paper, only steps (a) and (b) will be considered in detail. For the photoresist removal and cleans at (a) and (b), the vias and trenches in the dual-damascene structures must have smooth, non-bowed profiles that are free of etch residues upon which metallization will occur. In addition, the low-k materials should have no surface modification from the etch and clean processes that would change the effective intraline capacitance. The critical dimension of the via and trench features should also be maintained.

1. The processing sequence for each dual-damascene layer. A via-first scheme appropriate for an organo-silica glass is shown. The key steps where residues and contaminants must be removed are highlighted with a box. The bottom antireflection coating (BARC) is necessary for both lithographic and etch purposes.

2. Post-etch structure showing remaining resist and polymeric materials appropriate for steps (a) and (b) in Figure 1.

In the photoresist strip and clean in (a), changes in the critical dimension (i.e. the via size), the low-k material properties (e.g. the dielectric constant) and the via profile should be minimized. After the residue clean in (a), the trench lithography and etch steps are completed. The clean sequence in (b) is somewhat more complex. Here, the photoresist and polymer residues from the trench etch, plus any antireflection material used to print the trench and protect the barrier layer during the trench etch, must be removed. The barrier layer itself is then etched to expose the copper, and any subsequent etch-induced polymers are cleaned. Since copper is exposed during the barrier etch, the polymer film from the etch may contain sputtered copper. The acceptable residual level of copper contamination from the barrier etch after the clean has yet to be defined. Furthermore, the metrology technique that will be used to measure this low level of copper contamination within the small via (and trench) is not clear, and will need further development. In (b), no appreciable changes in the critical dimensions (i.e. via and trench), the low-k material properties and the via or trench profiles should occur as a result of the cleans and the etches.

After the clean in (b), thin-metal barrier layers and copper seed materials must be deposited. A clean, reproducible surface between the barrier and copper is required to give the best contact resistance. A smoothly deposited barrier metal is required to clad below the copper seed layer. Via and trench profiles, surface morphology and surface cleanliness are important for adequate barrier layer deposition. Beneath the barrier layer, the metallic surface contamination in the low-k material should be low, especially if there is any chance of mobility within the material. The cleans performed in the process sequence shown in (b) are probably the most critical because metal adhesion, metal barrier resilience, copper contamination, CD and contact resistance are all involved at that point. Finally, to complete the dual-damascene unit process, the clean shown in (c) is required to remove CMP-generated contamination and to produce clean, reproducible surfaces for the copper and low-k film prior to dielectric barrier layer film deposition, which protects the copper surface.

In Figure 2, the types of residues that would be encountered in the steps shown in Figure 1a and b are shown schematically. Etch residues from the patterning of OSG films will contain CF_x polymeric materials from the etchant chemistry, etch byproducts like SiO_x(F) and some fluorine incorporation into the resist structure.

3. A SEM showing a real example of a post-trench etch, dual-damascene structure. This is the situation shown in step (b) of Figure 1.

The materials schematically shown in Figure 2 are clearly visible in the SEM. The CF_x polymeric material on the horizontal surface will likely be quite different in chemical composition than the composition of the sidewall polymer on the vertical surface, because the horizontal surface experiences more ion flux bombardment than the sidewall polymer during anisotropic etching.

Figure 3 shows a SEM of a post-trench etch, dual-damascene structure in the OSG family of CORAL films¹ prior to the photoresist removal and clean sequence shown in Figure 1b. In Figure 3, as in the schematic view of Figure 2, several types of polymeric films have to be removed — the horizontal- and vertical-surface polymer films, unmodified photoresist and bottom antireflection coating (BARC). The objectives for the cleaning of this structure include the removal of the resist "crust" and etch polymer; complete removal of bulk resist (and BARC plugs); removal of polymer residues from surfaces and sidewalls; minimal damage to the low-k film; and no undercut of barrier or etch stop layers. All requirements must be met, but the need to minimize damage to the low-k film — particularly the dielectric constant — imposes constraints as to which residue removal chemistries are allowed. It is typical for the removal steps in Figures 1a and 1b to use both dry-clean (i.e. photoresist strip and residue removal) and wet-clean steps.² For the dry-clean step in the Iridia reactor,³ a reducing chemistry process is used to minimize the impact on the low-k dielectric constant.⁴

4. Infrared spectra of CORAL film subjected to a variety of rf or MW plasmas with oxidizing or reducing chemistries. (a) is the pre-clean sample; (b), (c) and (d) represent the OSG FTIR spectra after RIE/reducing, MW downstream/reducing and MW downstream/oxidizing chemistries, respectively. The film degradation clearly worsens from (b)—>(c) —>(d) as the OH content grows in the film, and the CH and SiC absorbances diminish. An rf process with a reducing chemistry impacts the carbon content of the film the least in (b).

Figure 4 compares the FTIR spectra of OSG films that are cleaned in a variety of dry-plasma chemistries. When cleaning residues from the vias and trenches, it is important to maintain the carbon content in the OSG film. The ratio of Si-C to Si-O absorbance in the infrared spectrum is a measure of the film composition, and is well correlated to the dielectric constant. Only the reducing chemistry of Figure 4b maintains this Si-C/Si-O figure of merit.

Figure 5 shows a dual-damascene structure in the CORAL where the etch residues have been removed by both plasma- and wet-chemistry steps. This is shown schematically in Figure 1b. The SEM in Figure 5a clearly shows photoresist, sidewall polymers and BARC layers from the lithography and etch steps as illustrated in Figure 1b. In Figure 5b, the structure has been dry- and wet-cleaned, and smooth surfaces on the CORAL are present.

5. Cleaning of the post-trench etch residues in a dual-damascene structure, i.e. the situation in Figure 1b.

The left image is the SEM of the post-trench etch structure with etch residues clearly present. Note the large residues inside the via. The right image is the SEM of the post-trench etch structure after a sequence of plasma and wet clean steps. Note the smooth surface of the CORAL film in the trench and via areas, proving that the residues have been removed. Dual-damascene schemes in low-k dielectric and copper have some challenging requirements for residue removal during the sequence. Acceptable solutions to the cleaning of these residues exist for the current technology node, but the continued need to lower dielectric constant, and for smaller dimensions and thinner barrier layers, will continue to promote intense development. Some development of the metrology for the measurement of metal and polymer contaminant levels on via and trench walls will be required.

Graham Hills leads R&D as vice president and general manager of Novellus' Surface Integrity Group. He came to Novellus through the acquisition of Gasonics, where he served as chief technical officer. He previously worked at Lam Research, where he spent three years as vice president/director of dielectric etch technology programs. He also spent seven years at Applied Materials, most recently as director of the silicon etch product unit. He holds a doctorate in physical chemistry and a bachelor's degree in natural sciences, both from Cambridge University.

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REFERENCES

1. CORAL is a trademark of Novellus Systems Inc.
   
2. A good review of back-end wet processing can be found in Y.S. Obeng and R.S. Raghavan, "Science and Technology of Semiconductor Surface Preparation," MRS Symposium Proc., Vol. 477, 1997, p. 145.
   
3. E. Pavel, "Plasma Etching for Sub-Quarter Micron Devices," Proc. Electr. Chem. Soc. (D.W. Hess, Y. Horiike and G.S. Mathad, eds.), 99-30, 1999, p. 34.
   
4. R.A. Shepherd et al, "Low and High Dielectric Constant Materials: Materials Science, Processing, and Reliability Issues (5th)," Proc. Electr. Chem. Soc. (R. Singh, H.S. Rathore, R.P.S. Thakur, C.C. Schuckert and S.C. Sun. eds), Spring 2000.
   

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