Defect Reduction in a High-Volume Fab
Chen-Ting Lin, Chih-Ching Lin and Jau-Jey Wang Taiwan Semiconductor Manufacturing Co., Hsinchu, Taiwan Yaniv Brami, Christophe Fouquet and Ariel Ben-Porath Applied Materials Israel Ltd., Rehovot, Israel -- Semiconductor International, 7/1/2001
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Achieving entitled yield quickly, and maintaining it in an environment that is characterized by a substantial number of products ramping up at any given time, is extremely challenging. Yield and random defect learning cannot rely on large amounts of statistical data, collected over extended periods of time. The accumulated fab knowledge must be incorporated into rapid control loops, which facilitate quick identification of killer defect sources, and allow tight control of process tools and process integration.
Excursion monitoring
| 1. Class partitioning by defect/step matrix. This matrix specified, for every process step, the associated defect types (classes) and their kill ratios. |
Once an out-of-control lot has been detected, a yield excursion is suspected, and the lot will be routed to a review station. Defect images are used to verify the existence of the excursion, and the defects are classified, usually according to a pre-defined scheme that is based on accumulated defect knowledge.
With current device geometries, scanning electron microscope (SEM) review tools have become essential because critical defect sizes are below the resolution power of optical microscopes. Automatic SEM defect review is gradually replacing the mundane task of manual review, driven by its consistent classification at very high throughput.
Achieving and maintaining a stable yield level is extremely important for a foundry to meet its delivery commitments. In contrast to a single product fab, in which pushing additional material can compensate for yield fluctuations, product life in a foundry is limited, and the fab cannot afford to wait for final yield tests. It is therefore extremely important to maintain a stable and predictable line yield across all products sharing the production line at any given time.
| 3. Class trend charts for two representative killer defects at the plug barrier inspection step. The chart shows that ADC output is highly correlated with expert manual classification over an extended period of time. |
However, many defect generation mechanisms give rise to a gradual increase, or trend, in the density of a specific class of defects. Since the total defect count represents several populations of defects, the trend in a single population is often masked by the random fluctuations until it is sufficiently large to trigger an alarm. A second drawback of the approach stems from the fact that wafers from multiple process tools are indistinguishable at the inspection station, masking tool variations.
These drawbacks have prompted Taiwan Semiconductor Manufacturing Co. (TSMC) to develop a methodology that provides a process baseline defect control, with much higher sensitivity and early detection of defect trends. This methodology also implements a tool-monitoring scheme, in which in-line SEM-ADC output is combined with lot history to provide process tool defect signatures.
In-line ADC methodology
Many random defect excursions are a result of an underlying degradation or drift in the performance of a specific component or material. Such excursions initially appear as a gradual upward trend from the mean density for the specific class of defects, later developing into full-blown excursions. To detect these excursions early, it is necessary to monitor the defect density of each of the killer classes separately.
| 4. Results for a single recipe, shown after data collection from five different products. Automatic defect review (ADR) accuracy measures the percentage of defects correctly redetected, and automatic defect classification (ADC) accuracy measures the percentage of defects correctly classified. The consistency of the results across different products was high, facilitating the master recipe approach. |
The strategy that was developed encompassed four major phases:
• A defect characterization phase, in which defects from key process steps were prioritized and related to specific process steps and root cause mechanisms.
• An inspection and review sampling strategy that optimized killer defect capture.
•A set of SEM-ADC recipes for the target layers. A modular structure was used to enable a single recipe for multiple products.
• A set of statistical analysis charts that allow visualization of defect class trends, and correlate the SEM-ADC output with specific process tools.
In phase 1, the extensive knowledge of yield and process engineers regarding defect types, their root cause mechanisms and kill ratios was captured and used to select the target defects. The main driver in this stage was the potential yield impact of each defect class. Three inspection and review points were selected for this study: poly gate etch, glue layer deposition and metal etch. Each of these points covers a sequence of process steps that were identified as significant contributors to defect limited yield loss.
The defect data were captured in the form of a defect-step matrix (Fig. 1). This matrix specifies, for every process step, the associated defect classes and a "killer" designation. Defects with sufficiently high kill ratio were designated killer defects. High-resolution multiple-perspective SEM images were used to identify each category, and the matrix was used as the master guide in creating ADC recipes.
| 5. A trend chart for a single killer defect class. The excursion on day 20 is already visible as an increasing trend, starting on day 17. However, the total defect count remains stable throughout this period, indicating that it is not sensitive to this particular class. |
The manufacturing execution system (MES) flags specific lots for inspection, based on this ratio, in addition to other determining factors such as product volume, entitled yield and other factors. The same lots and wafers are inspected at each point, allowing the defect management system to perform added defect computations, thereby ignoring defects carried over from an earlier inspection step to a later one.
A second flag defined in the MES routed a subset of the inspected wafers to subsequent review and automatic classification by the Applied Materials SEMVision cX defect review SEM. The size of this sample was determined by the lot review ratio.
Traditionally, manual SEM review has been performed on relatively small defect samples — up to 50 defects — because of relatively low throughput of labor-intensive manual classification. This was sufficient when used in conjunction with optical review, and for investigative mode, in which an excursion had already been detected.
For the adopted strategy of in-line ADC, a larger defect sample was found to be more cost-effective. The benefits of increasing the number of sampled defects far outweighed the additional review time because the lot had already been intercepted and routed to the review SEM. The larger sample was found to improve the accuracy of the derived statistical estimators, and an optimal sampling plan was created with the following characteristics:
• A maximum sample size of 150 defects was imposed.
• Samples from two different size bins were combined, with weights related to the size.
• Samples from clustered defects were considered separately.
For ADC output to be valid, class counts must be normalized according to the total defect count and the actual sampling plan. This normalization was carried out, and population parameters were derived from the sample statistics.
In phase 3, classifiers were built for three target steps, using SEMVision JET, a rapid setup package for ADC. The classification was optimized for those defect categories that had previously been marked as killers. Six to nine classes were defined for each review step, and used in the setup of the rule-based classifier.1
In the context of a pure-play foundry, where a variable mix of products is processed, ADC setup and operation must be independent of product design.
ADC recipes must be associated with an inspection and review step, and portable across all products. This was made possible by the modular structure of the recipe generator, which allowed a single master recipeto be used for all products.
Specific product information — namely die sizes and alignment targets — was stored in separate library objects for each product. Figure 2 depicts a diagram of the recipe structure for a single ADC step.
In the final phase, a set of control charts and limits based on ADC output was implemented. Following our overall strategy of increasing the available sensitivity by monitoring class trends for specific killer types, class trend charts were implemented for each of the relevant classes.
By monitoring each killer class separately, tighter control limits could be implemented. Control limits and corrective action procedures were defined and initiated for each chart. An example for such a chart is given in the next section.
In a high-volume manufacturing environment, each process module contains multiple identical process tools, in order to achieve the required capacity, as well as sufficient tool redundancy. To further enhance the quality of monitoring and achieve higher overall equipment effectiveness,2 class trend charts were combined with the lot history data, to produce tool trend charts, for specific killer classes.
Since the class partitioning was derived from the class-step matrix (Fig. 1), each killer class could be associated with a candidate tool set. In a tool trend chart, density data for some class X was plotted, for all lots processed by an individual process tool A, associated with this class.
The merging of killer defect density data with lot tracking history enabled a range of enhanced analysis methods, including an effective form of commonality analysis, process capability plots, and the ability to generate tool box-plot charts, as shown in the next section.
Results
| 6. Two examples of a tool trend chart. Each tracks a single killer defect class and a single process tool. This highlights defect trends that are related to a specific process tool drifting out of its process window. Such trends can easily be overlooked with trend charts that combine data from multiple sibling tools. |
To validate ADC performance, each wafer was also reviewed and classified off-line by a human expert, and the defect counts for each class and each lot were recorded. Two types of analyses were carried out on this data in order to quantify the long-term stability of the ADC and its portability across different products.
For each class, the ADC and expert count were charted and compared (Fig. 3), and the correlation coefficient between the two series was computed. These coefficients were in the range of 0.94-0.98 for different classes, providing a high level of confidence in the ADC stability and consistency.
To measure the performance of ADC across the different products, ADC accuracy was computed for the accumulated lots of each product separately, and found to be within 5%. Figure 4 shows these data for the plug barrier level.
Class trend charts were created for all killer classes, facilitating the setup of class control limits and associated response procedures for each class violation. An example of such a chart is shown in Figure 5, demonstrating a class excursion that was associated with a severe yield problem and not detected by the total defect count. The figure clearly shows the moderate trend in defect density associated with this excursion.
Extracting lot routing information from the MES and superimposing it on class trend charts was used to create tool trend charts for several process tools. This provided evidence for degradation in the defectivity levels of individual tools (Fig. 6).
| 7. Box plot chart for four photolithography tools, showing the median and distribution of defect density levels. The tools should ideally produce similar levels of killer type B, but tool 2 exhibits much higher defect levels. By periodically reviewing simi lar charts, baseline improvement activities can be directed toward the low-yielding tools. |
Summary
The methodology presented here establishes a framework for improved productivity in a high-volume, multi-product environment that is typical of a modern foundry. The work resulted in a novel model for process control with in-line automatic defect classification linked to lot history data that has a clear improvement index and yield rewards for the fab. In-line ADC was shown to be an effective strategy for fast feedback control, in conjunction with killer defect trend charts and lot history data.
Implementation of this methodology provided the yield group with consistent and reliable data that were used to effectively drive process groups toward increased productivity. The ability to provide solid evidence, based on defect partitioning and classified defect density, allowed monitoring of specific process tool performance, improvement of maintenance schedules and enhanced control of process modules. As a result, the fab was able to enhance overall equipment effectiveness, shorten response time, and improve profitability.
Contact Information
Ariel Ben-Porath, Applied Materials
e-mail: ariel_ben-porath@amat.com
J.H. Tzeng, TSMC
Phone: 1-886-3-5675020 x.3338
e-mail: jhtzeng@tsmc.com.tw
REFERENCES
- S. Somekh, "Increasing Overall Equipment Effectiveness (OEE) in Fab Manufacturing," Semiconductor Fabtech, 10th Ed., July 1999.
- A. Ben-Porath, T. Hayes, A. Skumanich, "Advanced Process Development and Control Based on a Fully Automated SEM with ADC," Advanced Semiconductor Manufacturing Conference, 1999.
The authors would like to thank many employees of TSMC for their contributions to this study, in particular Huan Chi Tseng, Wen-Kai Wan and Oliver Hsin Hu, whose support and guidance were instrumental. Tony I. Chen, Hawk Yang and Arye Meir of Applied Materials are also acknowledged for their time and effort.
