Defect Inspection Enters Integration Era
Alexander E. Braun Senior Editor -- Semiconductor International, 7/1/2001
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Ariel Ben-Porath, global marketing director for defect review systems at Applied Materials (Rehovot, Israel), sees integration as a trend. "There's an increasing level of integration into production, both for inspection tools and review tools," he said. "Everyone recognizes that for 0.13 µm copper process, SEM review is essential. An inspection and review plan is integral to production, as part of the everyday running of processes, yield maintenance and wafer throughput."
Andy Pindar, vice president of the yield enhancement group at Schlumberger (San Jose), sees a migration of e-beam tools from a 1-3 cm2/hr throughput level to the 10-20 cm2/hr area. "Today e-beam is used in module development, process integration, yield ramp-up areas. For example, a key use has been in the understanding of the defect evolution in copper dual damascene. Here, e-beam has been very effective in monitoring defects such as copper voids and CMP residue."
Copper and 0.13 µm
Before investing in copper, warns Pete Nunan, vice president, strategic alliances at KLA-Tencor, chipmakers should ensure that their yields are comparable to 0.18 µm aluminum. "If it isn't yielding, you need to know the root causes. Time-to-root-cause is key to overcoming defectivity."
Nunan also pointed out that aluminum works because of the industry's ample experience. "As a defect is captured on an inspection tool, our previous experience with aluminum enables us to rapidly determine root cause; but that is not yet the case with copper." Like others, KLA has developed techniques to understand issues that must be resolved for copper.
When dealing with seven metal levels, there is no tolerance for missing one excursion. Chipmakers do not like to hear that 100% inspection in copper CMP is necessary — it sounds too much like development. However, successful Cu manufacturing has been demonstrated using significantly higher sampling compared with aluminum.
Cu voiding is a critical problem for 0.13 µm. This is not a matter of tool-induced defectivity, but of the interaction of processes with small windows. For example, one copper voiding issue can be traced back to mask-making. A subtle via dimension variation on the mask propagates to photolithography, etching a slightly smaller via that makes it more difficult to sputter the barrier seed down its sidewalls, which then leads to electroplating voids.
"Voids can result from etch residue, mask errors, plater problems or a PVD particle," Nunan said. A high-speed scanning voltage-contrast e-beam system is required to be able to rapidly inspect billions of vias for void detection in order to get feedback and necessary statistics.
There are still three contenders for low-k integration: OSG films (Black Diamond and Coral), and SiLK from spin-on polymers. "Nothing's shipping in volume yet," Nunan said. "We're seeing things like via poisoning, where outgassing from those films interacts with DUV photoresist, making it pre-expose.Other issues such as slurry interactions on the low-k film, and differences in film thermal expansion coefficients cause adhesion defects." (Fig. 2)
It is not enough to inspect and find defects — yield killers must be found. ADC and defect filtering will become increasingly important. "It's no longer sufficient to produce a map with 10,000 small dots on the wafer and tell you there's a problem," Nunan said. "I must be able to say, Here's the filtered map, and these are the 300 defects you must focus on.' Automating this is the key to successful yield management."
The automation imperative
Inspection systems must operate as production tools. "With 300 mm, automation is obligatory," said Applied's Ben-Porath. "We're working with users to ensure that 300 mm standards — still somewhat fluid — include inspection and review tools."
Tool vendors must deliver not only systems, but also methodologies and solutions. With SEM defect review, the first important trend was process automation, and now it is accepted as an automatic part of production. These tools deliver defect classification, but vendors are now expected to tie this to defect knowledge, root causes and ultimately corrective actions.
Many applications require e-beam's voltage contrast capability to detect defects, yield killers in copper interconnect. "You don't need a large area scan to find them," Ben-Porath said. "We're defining methodologies where test structures are used to allow the capture of the same kinds of defects while keeping to a relatively small area — SEM review applied to SEM inspection."
While current systems will work at 0.07 µm, it is not clear what will happen beyond. Methods for enhancing SEM resolution exist. At the 0.07 µm node, killer defects will be 0.05 µm, and current applications such as X-ray spectroscopy will be complicated to use or will run out of steam, requiring the support of other methods such as Auger spectroscopy.
Joe Danko, vice president of engineering at Inspex (Billerica, Mass.), believes high-speed inspection systems must provide comprehensive data, combining sensitivity and throughput specs with defect information such as characterizations of types and potential sources. "Darkfield inspection faces challenges with defect scatter and size," Danko said. "It's exponentially more difficult to find smaller defects while maintaining high-speed inspection." The biggest hurdle lies in leveraging the usage of light for detection of defects 50 nm and smaller.
Litho and "pig poop"
As features go subwavelength, process window failures increase. Process window shrinkage is causing sensitivities in both micro and macro scales, such as in resist thin uniformity and bake uniformity. "With DUV, it was discovered that amine contamination triggers defect mechanisms in chemically amplified photoresists, reducing sensitivity," said KLA's Ashkenaz.
(As an aside, it is interesting to note that, when ASML developed 248 nm, it found that this condition — called T-topping — prevents the resist's top surface from properly printing the pattern. It was getting T-topping but did not know why. Then someone came across a Dutch government publication that tracks methane concentrations in the atmosphere, principally emanating from pig manure. This led to a scholarly study on the "pig-poop factor," examining the correlation between methane concentrations and T-top problems.)
As we progress toward OPC, defects become more significant and phase-shift masks have their own defects. Similar problems plague reticles. "You use a reticle a few times, then the question is whether it has degraded," Ashkenaz said. "Degradation can originate from migrating particles hidden somewhere within the volume under the pellicle, crystal growth in the pellicle adhesive, or chrome-damaging static discharge."
EUV lithography has other problems. "You can't use a pellicle with EUV, so removable pellicles are being considered," Ashkenaz said. No pellicle material has yet been found viable for 157 nm. Possibly glass or quartz with an index-matching fluid may offer a solution — a technology the industry has never used.
In process development it is necessary to be sensitive to all defect types and sizes. "There's a technique called photocell monitor — resist on silicon or resist on oxide on silicon — optimized for sensitivity to litho defects," Ashkenaz said. "It uses a high-resolution image processing system, since a laser-scattering system would miss some defect types."
The platform is used for process development, but also provides ongoing litho cell monitoring. "These tests are run daily on each path through the litho cluster," he added. "If the track has two spin cups, it's done for each critical layer resist in each cup. It might be done on four wafers daily per litho cell. Then it can manage the critical defect density baseline and identify those defects you must manage and track on a production basis with the photocell monitor."
E-beam sensitivity considerations
E-beam has proven itself for critical layer inspection, where killer defect mechanisms are otherwise invisible. "Here, voltage contrast is a huge advantage," said Schlumberger's Pindar. "If you see a defect in electrical test that seems to be a yield hit, you can correlate it with electrical problems that you detect using EUV inspection and voltage contrast."
The typical operating point for 0.10 µm sensitivity is about 10-20 cm2. "Some modes are faster, making them useful in applications where geometries are larger and it's possible to trade off sensitivity for speed," Pindar said. "If you go from 0.10, 0.20 µm or larger, your throughput rises by 2 to 4× since it operates on a square law."
The fundamental limit is beam current — a signal-to-noise issue. When it scans faster, the system delivers fewer electrons to the wafer. Eventually, a limit is reached. As Pindar puts it, "There's a beam current limitation. If you have 100 or 200 nA of beam current, you can go just as fast and can get a good signal from that — any faster and performance degrades."
Coping with electrical defects
"Parametric test was more of an electrical process monitor," Merkel said. "Now there's a middle ground where an electrical defect creates a point problem, either in reliability or in the circuit." For a user there are two concerns. One is the awareness of the electrical defect issue. The second is treating this as a defect problem, integrating it into the yield management process.
"In the past, defect analyses were focused on contamination from external sources," said Charles Thomas, president and CEO of Solid State Measurements (Pittsburgh). "Today's mini-environments are virtually particle-free, wafer transports are good, gas lines are clean, and both production gases and chemical supplies are very pure. Except for some abnormal event, everything in the production process is clean, and externally generated contamination defects are no longer routine, but unique, events."
Some measurements are hitting fundamental limitations, both in particle detection and gas and chemistry contamination. "Electrical defect measurements have moved from measuring externally generated contamination to measuring the thickness and other electrical parameters of ultrathin silicon dioxide and silicon nitride gates, high-k gates, low dose implants and low-k dielectrics," said Thomas. "Implant uniformity across a 300 mm wafer is a particular problem. Also, new low-k materials and processes must be routinely checked for both electrical and physical performance."
For thin gates, the trend is away from an optical toward electrical test. "For several years the corona technique was a very successful method for contamination monitoring, but it has limitations," said Thomas, adding that it has difficulty in measuring very thin, leaky oxides. "Also, it is only suitable for monitor wafers, limiting its usefulness as an in-line production tool."
SSM's electrical metrology systems use a small-diameter, non-destructive elastic probe to perform electrical measurements on production wafers. "We're creating a 30 µm-diameter MOS gate within scribe lines and measuring directly on the dielectric," said Thomas. "Many of the data correction required for large contact areas disappear, enabling accurate measurements of thin, leaky oxides. We've measured gate oxides as thin as 9 Å and see this technology as a way to make non-destructive electrical measurements on production wafers with throughputs in excess of 60 wph."
Optical inspection perseveres
Regardless of dire predictions, optical inspection endures. "Some fab engineers consider SEM review with ADC state of the art," said Thomas Breser, Leica Microsystems' (Allendale, N.J.) global marketing director. "For others, state of the art is off-line optical ADC, with new technologies such as UV ADC and DUV ADC, allowing the characterization of critical defects at the 0.13 and 0.10 µm technology nodes."
Optical detection and classification challenges are new materials, smaller dimensions and larger wafers. "With 300 mm wafers you encounter more defects, but you still want the same amount of chips or more out the door," said Breser.
Here, optical ADC offers significant benefits. "It has a higher throughput than SEM-based systems. Color information, for example, is invaluable in making accurate defect classifications, and SEM provides monochromatic information only." There are defect types — embedded and top surface defects — detectable with optical but not with SEM-based systems, making optical review and ADC a complementary resource.
Tom Verburgt, CTO at August Technology (Bloomington, Minn.), has a different perspective. "Our optical defect inspection equipment is aimed at defects 0.50 µm and larger. Our applications are different than those that some of the traditional inspection vendors go after. Defect size isn't our frontier — our challenges lie in new applications and non-traditional device types."
August's concentration is on flexibility. "Our goal is to wrap ourselves around more device types and applications," Verburgt said. "The trend has been to take defect inspection systems and add capabilities for high-speed metrology for applications such as bump inspection, probe mark inspection, high-speed CD inspection on MEMS devices where you're not just looking for pattern defects but doing metrology and comparing tolerances."
August views its future in device types and applications such as those in the optical market — optowafers — small and narrow devices. "Some of the different geometries and features that we're seeing on optoelectronic devices require flexible tools," Verburgt explained.
Integrated inspection and metrology needs are increasing exponentially. The ability to provide inspection capabilities to a process tool and furnish rapid feedback into the process line is crucial. The industry has not had much direct metrology feedback into process tools. This is changing and many of these capabilities will go into in situ or at least in-line with automatic feedback.
Quality Assurance for Flip-Chip and Wafer-Level CSP Mark Moore, There are several process points where quality control for flip-chip and wafer-level chip-scale packaging may take place: whole wafer, sawn wafer in film-frame, and die sorting from film-frame. Major inspection criteria include defects within active die area, two-dimensional and three-dimensional bump inspection, chip-outs and cracks. Typical active die defects are scratches, particles, contamination, passivation, metal and resist. When it comes to bump inspection, there are different opinions about the inspection that is required. All agree that 2-D is a must for diameter, position and damaged bump. But ideas vary on 3-D bump inspection. For 300 µm bumps or larger, 2-D may suffice. As bumps get smaller, the tolerances (10-20 µm) are tighter for height and coplanarity. Without 3-D, there is more vulnerability to escapes. The recommendation is to have inspection capabilities for all of the bumps. As the bumping process proves out, a sampling percentage plan may apply. Inspection normally takes place at the very last point before the wafer leaves the facility to go to the customer. For many, it will be at the die sorting step. By combining high-resolution inspection onto a die sorter, the result is a productivity tool that also serves as a process control tool. These new systems are just now coming into the marketplace. Selection should be based on a system that is easy to use, has self-teaching to eliminate operator subjectivity, and can accommodate process variations.
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