Minimizing Process Control's Effect on Cycle Time
-- Semiconductor International, 5/1/2001
A logical target of cycle time reduction is the photolithography bay because steppers are often the bottleneck tools, making them rate limiters in overall fab cycle time. Factors that influence cycle time include test run procedures and duration, whether or not steppers are dedicated to critical levels, and the duration of inspection times.These are some of the factors that researchers at Hitachi Ltd. (Tokyo) and Purdue University (West Lafayette, Ind.) explored when they studied cycle time issues associated with process control steps in a paper published in the February IEEE Transactions on Semiconductor Manufacturing. Using simulation, the group determined that inspection times have the greatest impact on cycle time performance. Furthermore, long, infrequent machine downtimes increase cycle time significantly, but can be offset by not dedicating certain steppers to critical levels. Test wafer procedures do not generally affect cycle time very much, unless the lot is put on hold while the test wafer is reworked. The group found that optimal cycle time is attained when test wafers are inspected in parallel with the processing of other wafers in the lot.
The researchers used a simulation model that was developed using SIMAN and was supported by a Unix C language insert. They assumed a DRAM fab with several separately modeled stations (lithography, ion implant, etching, etc.), each following first-in first-out (FIFO) rules except for the photolithography module. Wafer start level is constant at 500/day, and lots arrive at the module every 72 min. Importantly, the model does not account for operators, precleaning operations and lot transportation. The model's primary performance measurements are the average and coefficient of variation of lithography cycle time and fab cycle time.
The researchers investigated three scenarios (policies) for test wafer processing:
- Policy 1 -Test wafer joins its lot after rework. If the test wafer passes inspection, the stepper is qualified, the lot is processed and the test wafer joins the lot. If the test wafer does not pass inspection, it is stripped while the stepper is adjusted. Upon a successful test run, the stepper processes the lot and the lot waits for the test wafer to be reworked.
- Policy 2 -Test wafer forms a new lot for rework. The same as policy 1, except the test wafer is stored in a separate cassette until 25 test wafers are collected and reworked.
- Policy 3 -Test wafer is reworked with its lot. Wafers in the lot are processed even if the test wafer fails inspection. The entire lot is then stripped while the stepper is adjusted, and a second test run takes place. After stripping, the lot is reworked.
In addition to the three test run policies, the model accounts for two machine dedication policies (some critical-level steppers or all steppers process all mask levels) and two inspection times (10 or 20 min/wafer). It also considers two levels of stepper failure rate (0.5 or 2%); two breakdown scenarios (MTTF of 43,200 hrs/MTTR of 864 hrs and MTTF of 10,800 hrs/ MTTR of 216 hrs); and two levels of test run frequency (every four or every eight lots). By isolating controllable factors - including test run policy, machine dedication policy and frequency of test runs - a fab manager can determine when changes in maintenance management or inspection equipment purchases need to be made.
Modeling shows that the Policy 1 test run has the longest cycle times (because of longest test runs), and Policy 3 has the shortest. The non-dedicated stepper approach leads to shorter cycle times and reduces the adverse effects of tool breakdowns; however, effects on yield may prevent elimination of a dedicated stepper policy. Not surprisingly, infrequent breakdowns with long repair times greatly increase both the photo and overall fab cycle time; therefore, more frequent, shorter breakdowns are preferred.
For all test runs and stepper dedication policies, cycle time was most affected by the inspection time. Interestingly, stepper failure rate becomes significant only under Policy 2. The Policy 3 test run features the shortest cycle times, followed by Policy 2. With Policies 1 and 3, all wafers in the lot move together during the entire fab process, making the attribution of defects detected at wafer probe easier to trace. Assuming wafers should stay together, depending on WIP, the fab manager may be compelled to switch between Policies 1 and 3. However, the researchers concluded that Policy 3 was still best under all circumstances because of the high overall cycle time associated with Policy 1. This study also showed the importance of reducing inspection time (increasing the efficiency of metrology tools) because of the great impact on cycle time.
- Laura Peters
