Using a Learning Machine to Control Key Yield Metrics
Laura Peters, Senior Editor -- Semiconductor International, 5/1/2001
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The group at Agere first identified 22 key process steps and one yield step that most impact effective gate length (Leff), poly linewidth, Ion and Isub. These include the threshold adjust implants; source/drain and LDD implants and associated anneals; patterning steps for poly gate including hard mask; gate linewidth measurements; and IV measurements. In modeling the transistor yield, the group defines a transistor "minifab" — a cluster of processes that most influence yield — which can be considered independent of other modules (such as a via minifab). This approach helps determine the driving factors for Leff, poly linewidth, Ion and Isub, and how these metrics change from month to month, product code to product code, lot to lot and tool to tool.
The engineers extracted portions of a 1995 database containing information on 0.5 µm products across nine technologies and containing up to 55 parametric measurements (film thickness, sheet resistance, linewidths, etc.) and 23 IV test measurements, along with tool IDs, operator IDs, dates, etc. The group combined the SPC files (ASCII flat files) with a lithography database with pattern density information, and preprocessed the information so that all data associated with one lot and one processing step was recorded in one record — resulting in a file with 5646 unique lots and 111,117 records. After assigning binary vectors to represent many of the parametric values and IV values, the data were partitioned into inputs and outputs, which would then be normalized on the fly by the learning machines during processing.
The engineers next conducted cross-correlation, autocorrelation and probability distribution studies for all the variables. After gaining an understanding of the data's behavior, the group chose a learning system model that essentially maps the inline parametric measurements to the yield metrics for the minifab. The model is capable of quantifying the impact of inputs on the main output, Leff, while minimizing chances of compounding errors.
The yield parameters are represented by 131 inputs and 11 output values. Viewing the inputs as clusters, there are 22 sets of 25 scalar elements representing the inline measurements and the associated binary vector for gating the inputs, giving a total of 550 inputs. A gating network determines which outputs to feed forward and which to feed back for model training. It uses weight regulation to reduce complexity and takes a learning-with-constraints approach.
After training the neural network using 5000 wafer lots, a sensitivity analysis revealed average RMS errors for the 11 outputs of 0.25, which tapered to 0.20 after 5 million learning iterations, implying 80% accuracy. The model was verified using two-thirds of the data for learning and one-third for verification.
Next, the model was used to conduct sensitivity analysis on new fab data. The group generated sensitivity curves for the 23 key process steps, and "tweaked" the values by incrementally changing the measured input values by 0.1, starting at -1.0 and ending with +1.0. Pareto charts based on the results identify the processing steps with the greatest impact on Leff and suggest the best current targets for advanced process control. For more information, see the February issue of IEEE Transactions on Semiconductor Manufacturing.
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