Barrier and Seed Technologies for Sub-0.10µm Copper Chips

		At a Glance
	As device manufacturers transition to the 0.10 µm generation, they are faced with the challenge of depositing barrier and seed layer films for dual-damascene interconnect structures. PVD will be extendible using self-ionized plasma. However, for sub-0.10 µm requirements, CVD methods become viable for the barrier film, particularly TiSiN.

The accelerated introduction of new device generations has highlighted the need for process equipment extendibility. Ideally, to minimize development time and implementation costs, deposition systems developed for Al metallization could also be used for the Cu barrier and seed layers. Physical vapor deposition (PVD) methods have been used for Al metallization for more than 30 years. For copper diffusion barrier and electroplating seed layers, PVD is extendible to the 0.10 µm device node by using second-generation metal ion plasma technology. However, below 0.10 µm geometries, the use of porous, extreme low-k materials with copper may require introduction of chemical vapor deposition (CVD) methods for the barrier layer — and perhaps for the seed layer — to meet the more stringent dimensional and integration issues. CVD barrier materials such as TiSiN have exhibited superior step coverage and the ability to integrate with next-generation low-k dielectric materials with current CVD deposition equipment.

Extending PVD technology

PVD technologies have evolved from thermal evaporation to sputtering to today's ionized metal deposition. With each shift in deposition technology, there have been process and hardware advancements to meet decreasing feature sizes and increasing aspect ratios. Each new device generation has required improved step coverage and reduced overhang (the amount of material deposited at the top corners of a feature, which limits the amount of material that can be deposited within the trench or via).

Beginning at the 0.18 µm device node, ionized PVD has evolved from ionized metal plasma (IMP) to self ionized plasma (SIP) to provide increased metal ion flux. By generating metal ions either by rf power (IMP)¹ or by the source design (SIP), the directionality of the ionized metal atoms can be controlled by the wafer bias. The Ar ions that reach the wafer are also directional and can result in resputtering of material from the top and bottom of the feature.

Wafer bias is very important in controlling both the flux of metal ions and the amount of resputtering. The neutral metal atoms are nondirectional and can cause overhang, since their deposition profile is determined by line-of-sight deposition. The role of metal neutrals and ions is shown schematically in Figure 1.

	1. The directionality of metal ions (M + ) controls step coverage, overhang and bottom resputtering.

The use of SIP technology takes advantage of the magnetron source design, which provides for efficient transfer of energy from the secondary electrons to the plasma waves to increase ionization of the sputtered metal atoms.²

The SIP source also allows for low deposition pressure(<2 mTorr), which in turn increases the mean free path. This results in less off-normal flux due to the decrease in scattering. The target-to-substrate spacing is increased to provide additional self-collimation in order to improve sidewall and bottom coverage. The SIP technology is used for both the barrier and the seed materials.

PVD barrier/seed materials

For barrier films, Ta and TaN have been implemented because of the specific film properties that are required for integration into the Cu metallization scheme. In addition to being good Cu diffusion barriers, Ta and TaN possess good adhesion to the dielectric and Cu, as well as good CMP compatibility.

A unique benefit of TaN is its good diffusion barrier property to F, whereas Ta will react with F. The Ta film, on the other hand, has the advantage of acting as a nucleation layer for Cu, enabling a (111) orientation, which is critical for reliability.³ To take advantage of each of the individual film's properties, a barrier structure combining TaN and Ta has been developed.⁴

SIP technology enables a stacked structure of TaN and Ta; the planar target design minimizes redeposition of the sputtered material, a critical aspect of maintaining low particle levels. Films of varying nitrogen content — including a nitrogen-rich TaN film of >30 atomic percent — can be deposited in the same chamber, which allows for tuning the nitrogen concentrations at the dielectric and copper interfaces.

Copper seed layers require a continuous film to carry current for the electroplating process. This demands adequate sidewall and bottom coverage in very small dimension dual-damascene structures. Increasing aspect ratios(>4:1, depth:width) decreases copper thickness inside the feature, and the film becomes more sensitive to temperature-induced agglomeration. Lowering the wafer temperature is critical to ensuring a continuous film.

As with barrier films, the use of SIP hardware allows for improved copper seed layer sidewall and bottom coverage. Target power and wafer bias both affect sidewall coverage (Fig. 2). The measured sidewall coverage is at a minimum for low target power and low wafer bias. For a fixed wafer bias, as the target power is increased, the ion metal flux increases in conjunction with the sidewall coverage. Increasing the wafer bias directs more metal ions toward the wafer.

The maximum Cu sidewall coverage occurs at high target power and high wafer bias, and is ~40% higher than the minimum as measured by transmission electron microscopy for the trench structure. By optimizing both the process and hardware, barrier and seed films with minimum overhang and high step coverage are achieved (Fig. 3). This optimization is critical for void-free electroplating copper fill.

	2. Sidewall coverage increases with bias and target powers.
	3. TEM cross section showing SIP Ta(N)/SIP Cu step coverage with minimal overhang.
	4. Tailored step coverage on high aspect ratio 0.10 µm feature using an advanced PVD source.
	5. Critical areas for step coverage in dual-damascene structures: shadowed area and unlanded via.
	6. CVD TiSiN (bottom) exhibits superior Cu wetting characteristics to CVD TiN (top).

To accommodate structures below the 0.10 µm device node, an advanced PVD source has been developed to further increase the ionization flux and, hence, step coverage. This advanced hardware will be prompted by the need to extend PVD to these smaller feature sizes. By increasing the ionized metal flux, the role of wafer bias is more critical in controlling the amount of deposition and resputtering. Step coverage on the horizontal and vertical surface features can be tailored by optimizing the sequence of different process conditions. An example of this technique is shown in Figure 4, where the field thickness can be minimized, with enhanced sidewall and bottom coverage.

Further extension of copper interconnect technology includes alloying the copper seed to potentially eliminate the barrier by creating a self-passivating diffusion layer. One example is Mg, which will segregate to form a very stable copper/dielectric interface.⁵ There is also the potential advantage of introducing alloying elements that will increase electromigration resistance.⁶ In both cases, the amount of alloying material needs to be minimized to keep the Cu film resistivity as low as possible.

CVD for barrier/seed films

The extension of PVD has delayed the need for a CVD barrier and seed solution. However, PVD's limitations in step coverage and the introduction of porous low-k dielectrics may necessitate a transition to CVD barriers at or below 0.10 µm. The dual-damascene structure challenges PVD in providing adequate sidewall coverage in shadowed regions and continuous films for unlanded vias, as shown in Figure 5. The severe topography and atomic scale surface roughness of porous extreme low-k materials necessitates a conformal CVD barrier process.

A proven barrier solution is TDMAT (tetrakis dimethyl amino titanium)-based CVD TiSiN, which has demonstrated >90% conformal step coverage and Cu diffusion barrier properties equivalent to PVD Ta(N). CVD TiN-based material would be an ideal candidate because of its known manufacturing and integration capabilities in W liner applications. However, the properties of CVD TiN and other W-based films as a Cu diffusion barrier are less effective compared with PVD Ta and TaN films.

By introducing Si into the TiN matrix, the Si is bonded to the N, significantly improving barrier properties compared with CVD TiN. Existing CVD TiN hardware can be easily modified to deposit TiSiN.

TiSiN has the additional benefit property of good wetting to Cu. The wetting characteristics of Cu to the underlying barrier layer have been correlated with improved electromigration resistance.⁷ As shown in Figure 6, the thin Cu layer agglomerates for CVD TiN but not for the CVD TiSiN. Results shown are for 100 Å Cu film thermally cycled at 380°C for 15 min.

To validate the device integration of CVD TiSiN, electrical measurements were performed. Figure 7 shows the cumulative probability plot of the via resistance of a 0.22 µm via chain of 65,000 links for a 50 Å TiSiN film. Low via resistance comparable to SIP Ta(N) is achieved with good yield. Typical film resistivity is 350 µV-cm for a 50 Å thick film. Because TDMAT-based CVD TiSiN is conformal, the barrier film thickness can be reduced to achieve even lower via resistance.

Process repeatability tests were completed to validate reproducibility and particle performance. Thein-film particles measured at 0.05/cm² (>0.16 µm), indicating excellent control as a result of the optimized process conditions and chamber hardware.

	7. Equivalent via resistance for 50 Å TiSiN and 250 Å SIP Ta(N) for 0.22 µm 65K via chain.

The unique film properties of PVD Ta and TaN can also be integrated with CVD barrier films. Using a single multichamber platform, thin PVD Ta and TaN layers can be deposited with the CVD barrier material as an under- or over-layer to create the desired interfacial properties.

CVD for Cu seed has also been demonstrated. Although these films exhibit excellent step coverage, an underlying film to ensure adhesion is required. This additional adhesion process step makes the cost of this process sequence prohibitive.

Research for next-generation barrier and seed deposition technology is focused on evaluating atomic layer deposition (ALD) processes. ALD is based upon the sequencing of self-limiting reactions using different precursors, with the potential for controlling on a monolayer scale the composition of the films. The challenge with this technology is the choice of precursors to meet all required properties. Hardware is optimized to finely control the reactant introduction and byproduct removal; precursor flow and temperature uniformity are non-critical. ALD films are under intense investigation.⁸ However, an optimum precursor chemistry for barrier and seed has yet to be identified.

Conclusion

As device manufacturers transition to the 0.10 µm generation, they are faced with the challenge of depositing barrier and seed layer films for dual-damascene interconnect structures. PVD will be extendible using self-ionized plasma technology to increase metal directionality and step coverage. However, for sub-0.10 µm requirements, CVD methods become viable for the barrier film, particularly TiSiN, which offers effective barrier performance, excellent step coverage and the capability for integration with low-k dielectric materials. The challenge presented by the introduction of 300 mm wafers with the convergence of Cu metallization and extreme low-k dielectrics means that all deposition technologies must be available in both 200 mm and 300 mm configurations.

Barry L. Chinis senior director for the Cu barrier/seed division at Applied Materials, responsible for developing and commercializing barrier and seed layer films for Cu metallization. He received a Ph.D. in materials science and engineering from the University of California at Berkeley.

Gongda Yaois the general manager of the Cu barrier/seed division, responsible for both PVD and CVD technology and product development in Cu barrier and seed applications. He received a Ph.D. in materials science from the State University of New York at Stony Brook.

Jianming Fuis a director of core PVD technology, responsible for the development of new PVD technology and products. He received his Ph.D. in physics from Pennsylvania State University.

Peijun Dingis the PVD Cu barrier/seed technology director in charge of PVD technology and product development in Cu barrier/seed application. He received a Ph.D. in physics from the State University of New York at Albany.

Ling Chen is responsible for CVD/ALD technology and integrated CVD and PVD product development for the Cu barrier/seed division. He received a Ph.D. in physics from the State University of New York at Albany.

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Acknowledgments

The authors would like to acknowledge the technical contributions from the copper barrier/seed, PVD technology and SEM/TEM analytical organizations of Applied Materials.