Copper Interconnects for High-Volume Manufacturing

		At a Glance
	Copper technology is transitioning into high-volume manufacturing. Unit process concerns such as feature fill, film uniformity, defects and anneal are being addressed by equipment suppliers to optimize processes and integration schemes.

While the use of copper interconnects in semiconductors is no longer breaking news, the challenges facing industry leaders in taking copper damascene to high-volume manufacturing are nonetheless plentiful. Last year, the focus for chipmakers was on unit process optimization and on integration. Issues such as feature fill, edge and bevel cleaning, anneal and bath control were addressed through refinements and enhancements to semiconductor processing equipment. Integration schemes were developed to obtain yielding devices.

Now that many of the unit process concerns have been addressed by equipment suppliers — and several of the integration difficulties overcome by device manufacturers — what remains is the challenge of optimizing these processes and integration flows to obtain highly reliable devices with excellent yield in high-volume manufacturing. There are still issues that are being faced by the industry as copper interconnect technology is ramped for high-volume manufacturing.

The copper market

The use of copper is no longer dominated by semiconductor manufacturers in the United States; about half of the world's users of copper technology are now in Asia (Fig. 1). Most device manufacturers are employing a dual-damascene integration scheme with a via-first etch. Others have made their entry into copper with a single-damascene technology, choosing to sort out the copper manufacturing issues before moving on to a more complex integration scheme. There are about 22 semiconductor manufacturers worldwide engaged in the use of copper.

Early adopters of copper technology implemented copper in production at the 0.25 µm device node. Most copper in production or pilot production today is at the 0.18 µm and 0.13 µm technology nodes. For some manufacturers, 0.13 µm is a second generation of Cu; for others, 0.13 µm is the entry point for putting Cu into production (Fig. 2).

	1. Market analysis of device manufacturers using copper in production.

The challenges of implementing Cu at the 0.13 µm technology node are more demanding than at the larger technology nodes. Feature size and aspect ratios make barrier/seed deposition and fill more difficult. Smaller features require better defect performance, making yield issues more challenging. Shrinking dimensions and the need for improved dishing and erosion performance in copper CMP drive increasingly stringent uniformity requirements. Achieving good electromigration performance becomes more difficult. At 0.13 µm, many manufacturers are implementing new low-k materials that must be integrated as well.

About 40% of the total production of all logic devices will use copper technology at the 0.13 µm technology node. By the 0.10 µm device node, 90% of semiconductor manufacturing will use copper technology.

The wafer size transition from 200 to 300 mm for copper devices will occur this year, largely at the 0.13 µm technology node. By the 0.10 µm technology node, the majority of devices are predicted to be manufactured on 300 mm wafers. The applications served by this technology are advanced logic products, such as microprocessors and DSPs.

	2. Market analysis of device manufacturers using pilot production today.

The shift to copper technology for memory manufacturers lags that of logic by more than a generation because memory devices do not rely on interconnect performance, and the cost sensitivity of memory production demands that the technology be more mature prior to implementation. A similar argument can be made for the wafer size transition, though this transition will be driven purely by cost considerations. Some of the early memory adopters of copper technology will likely be those companies that manufacture both logic and memory devices. For these manufacturers, the memory technology uses the same back-end processes and tooling as the logic technology, but lags in timing and employs a reuse of the logic equipment as a cost advantage.

The state of copper technology

For the suppliers of electrodeposition equipment for copper interconnects, last year was focused on providing new capabilities for semiconductor manufacturers that were, for the most part, in the development phase sorting out their individual technology requirements for the integration of copper into their device structures. Some of these capabilities included better control of bath stability by the addition of closed-loop chemical monitoring with predictive dosing, addressing the issue of Cu cross-contamination, and getting 300 mm tooling ready for production. There was also a large focus on defects and driving root-cause solutions to enable yielding devices.

	3. Example of a "pit"-type defect. These defects result from inadequate surface wetting during the copper plating process.

This year's focus has shifted toward manufacturing issues that affect yield, as the semiconductor manufacturers move from development pilot line production to high-volume manufacturing. As a whole, the tools used for the manufacturing of copper devices are mature and have good reliability. The focus this year is on repeatable processes with excellent fill, low defectivity, good uniformity and high yields. This is the year that we will see the technology of copper really mature.

Feature fill, film uniformity

Generally speaking, feature fill was last year's problem. Improvements in PVD barrier/seed deposition and in plating chemistries have driven fill capability to easily extend to the 0.10 µm technology node, possibly even the 0.07 µm node. That said, there are several variables that must be closely managed to ensure a repeatable fill process.

The most challenging aspect of good repeatable feature fill is closely controlling the PVD barrier/seed process. A large overhang will cause pinch-off of the electrofill and void formation at the top of the feature. Step coverage problems along the lower sidewall will retard growth in that portion of the feature, allowing the feature to close off and leaving a void in the bottom. Symmetry issues in the PVD barrier/seed deposition process will result in having a much thinner sidewall than would otherwise be expected for a given thickness, which again could lead to void formation. Any discontinuities in the seed, such as agglomeration, cause the plating to be suppressed and a void to be formed. The agglomeration is not the problem in and of itself — it is the discontinuity that causes the void to be formed. Seed smoothness can affect plating by enabling an early pinch-off of the structure, resulting in a void being formed.

Controlling via shape is also important to repeatable feature fill when using a PVD barrier/seed. This can be a problem, particularly when trying to integrate an organic-based low-k ILD because of profile issues that arise during the etch process. Again, any discontinuity in the seed layer will affect fill. With adequate seed coverage, the electrofill process can easily fill re-entrant structures.

	4. Example of "missing metal"-type defects. These defects arise from grain pull-out or corrosion and are exposed during the CMP process.

Another area of importance from a manufacturing standpoint is control of the film uniformity. Managing wafer-to-wafer, within-wafer and within-die uniformity is also important, especially from a CMP standpoint. Copper CMP is a relatively immature process, and close control of the plated film is necessary to minimize the amount of overpolish required and the subsequent dishing and erosion. Some device manufacturers now specify an overall range for the plated film rather than a uniformity. Controlling the thickness profile for high wafer-to-wafer repeatability can be an enabler for the CMP process.

The control of within-die uniformity is also important. Dense patterns have the most acceleration or bottom up filling, while wide features behave like planar fill. The enhanced growth rate in narrow features is due to the accelerator. A large within-die non-uniformity causes problems with CMP because more overpolish is required for smaller features, resulting in dishing and erosion in the larger features. Within-die uniformity can be improved by modifying the chemistry to include a leveler, or by modifying the process to use a reverse pulse to desorb the accelerator.

Defects

As copper is moved into manufacturing, and with the implementation of copper at smaller and smaller device generations, there is an increasing focus on understanding and eliminating defects. Defect modes for a plated Cu process are quite different than those for a subtractive Al process. Device manufacturers and equipment suppliers have had a challenge in identifying and eliminating the major defect modes for the copper damascene process.

	5. Increase in ambient temperature stress of 1.0 µm copper film after a thermal cycle to the anneal temperature.

One of the most critical variables affecting the defectivity in the electrofill process is adequate surface wetting prior to initial deposition of the copper film. Wetting is highly dependent on plating chemistry, seed layer structure, composition, surface oxidation, contaminants, etc., as well as how the wafer is immersed into the plating bath and the plating is initiated. A common defect is the "pit" defect (Fig. 3). This defect is the result of inadequate surface wetting. "Pit" defects often show up as macroscopic swirls and are commonly found in lines of pits. Other wetting-related phenomena are also observed, some of which are macroscopic and can be seen with the naked eye. The larger defects can actually have a "tail," which is the result of a change in deposition rate from the local flow around an adherent bubble.

Other defects that are unique to copper manufacturing and that have plagued device makers are post-CMP or "missing metal" defects (Fig. 4). These defects, which are a result of corrosion or grain pull-out, are exposed during the CMP process and can be dependent on plating chemistry, plating waveform, barrier composition and thermal treatment. The mechanism for these post-CMP defects is poorly understood, but involves a complex interaction between grain structure, film relaxation and stress relaxation.^1,2 Small geometries and high-aspect-ratio features are particularly prone to "missing metal" defects, as are plating chemistries and processes that result in a large-grain microstructure. With the copper overburden in place, thermal excursions to high temperatures will also enhance this defect mode because high levels of tensile stress can result from such thermal treatments (Fig. 5).

	6. Increase in tensile stress after thermal cycle, which leads to stress concentration at top on trench and concentration of defects.

As geometries get smaller, the effect of the thermal treatment gets more pronounced. Figure 6 suggests a mechanism for the formation of via pull-out, which results in low via chain and device yields. As temperature is increased, the thermal expansion of the copper is greater than that of the surrounding dielectric film. This, in turn, induces compressive stress in the copper film that will recrystallize and relax through dislocation motion. Upon cooling, the copper will contract and go into a tensile stress that is much greater under ambient temperature conditions than the as-deposited film.

To reduce the occurrence of defects related to thermal treatment, it is necessary to minimize the temperature excursion with the copper overburden in place. Temperatures must be maintained below the plastic flow limits (~200°C) so the copper may expand and contract elastically. Controlling the microstructure and barrier composition are also important factors. Figure 7 shows the sensitivity of via chain yield to the post-plate anneal temperature with the copper overburden in place.

The control of defects related to the copper process is perhaps the single most important issue as manufacturers drive to get higher and higher yields for copper in production.

Reliability

	7. The effect of post-plate anneal temperature with the copper overburden in place on via chain yield.

The requirement for an anneal step has been driven by the need to stabilize the copper CMP rate, lower film resistivity and provide a consistent and optimum texture for electromigration resistance. But the question among semiconductor manufacturers is one of how much anneal, at what temperature, and for how long. As the story has unfolded, it is apparent that annealing is a very complex subject, with a balance between the need for good electromigration performance and the issues related to thermal treatment-induced defectivity.

From strictly an electromigration viewpoint, the higher the temperature, the longer the duration of the anneal (with the copper overburden in place) — and the better the electromigration performance of the device. This is especially true for the narrow linewidths associated with shrinking technology nodes.

Electromigration performance is related to the grain growth in the trenches. The kinetics of grain growth within a trench are highly dependent on the size and aspect ratio of the trench because of the physical constraints of the trench sidewalls. Large linewidth trenches will fully anneal at lower time/temperatures than narrow lines. Therefore, an anneal process that maximizes the grain growth, and hence the electromigration performance, of the narrow lines must be chosen.

	8. Electromigration lifetimes for narrow lines (0.35 µm) with various pre-CMP anneals. The anneal has a larger impact on the electromigration performance of high aspect ratio lines.

Figure 8 shows a comparison of the electromigration performance of narrow lines (0.35 µm) with various pre-CMP anneals. There is a balance between the deteriorating defect performance and the improved electromigration performance as the anneal temperature is increased. Manufacturers have found conditions where acceptable defect performance and acceptable electromigration performance are achieved and high-yielding, reliable devices can be manufactured.

Again, as with the defect story, the electromigration performance is dependent not only on the thermal cycling of the device structure but also on the microstructure of the plated film and the choice of barrier/seed. Many device manufacturers have struggled putting copper into production while they have worked through the issues related to defect performance and reliability. The knowledge gained by the industry over the past year will enable all of the late adopters of copper technology to put copper into production on a shorter development cycle.

Looking ahead

The issues that will face device manufacturers at the 0.10 µm node and below will be similar but more challenging than those encountered at the 0.13 µm node. As at the 0.13 µm node, barrier and seed coverage will be critical, especially if etch profiles are compromised with the introduction of new low-k materials. Electroless plating techniques may be an enabler for copper fill because they can "repair" discontinuities in the seed deposition, which will likely be an extension of PVD technology. Figure 9 shows an example of how a thin electroless layer can enable copper fill on structures with poor seed step coverage. CVD barriers will also likely be introduced at this technology node to deal with the step coverage issues and the thin barrier requirements for such small geometries. Another technology improvement that is likely to find its way into the 0.10 µm node is abrasive-free CMP slurries. Problems with dishing are almost non-existent with such slurries, and there may well be a cost advantage when these slurries are available from multiple chemical suppliers.

	9. Fill results for vias seeded with discontinuous PVD copper and ECD (above) and discontinuous PVD copper and electroless copper film plating.

New low-k materials and smaller geometries with higher aspect ratios will likely limit the anneal temperatures possible without creating defects. Fortunately, the introduction of CVD barriers may help in this area, as early results show an improvement in typical pull-out type defects — including via pull-outs — as well as improved electromigration performance. Still, as geometries shrink it will be necessary to drive defect performance down further. Many device manufacturers have "zero defect" programs in place now.

Early adopters of copper technology implemented processes at the 0.25 µm technology node. Today, device manufacturers are at the forefront of transitioning copper technology into high-volume manufacturing for the 0.13 µm node. By the 0.10 µm node, the majority of devices are predicted to be manufactured on 300 mm wafers. Many of the unit process concerns such as feature fill, film uniformity, defects and anneal are being addressed by equipment suppliers. What remains is the challenge of optimizing these processes and integration schemes to obtain reliable devices with excellent yield. The copper ramp has started for many of the top semiconductor producers, with yield goals approaching equivalency to aluminum technology.

Optics, Eddy-Current Measurements Provide Optimum CMP Process Control-- Peter Nunan, Vice President of Yield Technology Solutions, KLA-Tencor, San Jose

Once a technology that many thought would never see the light of production, CMP has now become a great enabler of the microelectronics revolution. However, integrating CMP into high-volume manufacturing has its hurdles. These include monitoring oxide and tungsten CMP removal rates, controlling CMP uniformity, and controlling oxide and tungsten CMP defectivity. And, as the industry progresses down the ITRS Roadmap, additional challenges arise from the transition from aluminum to copper interconnect; from standard k material, such as fluorinated silicate glass, to low-k materials, such as OSG or SiLK; and from 200 mm wafer size to 300 mm. One of the biggest difficulties today is achieving better control of metal dishing and dielectric erosion in the copper CMP process. The source of the challenge lies with copper electroplating, as wafer thickness and within-wafer thickness uniformity can vary significantly. Chipmakers are faced with the problem of compensating for these variances in order to achieve the desired polish results for each wafer during CMP. Better control of metal dishing and dielectric erosion is crucial in the copper CMP process. One way to accomplish this is by dynamically compensating for variances to achieve the desired polishing results. (Source: KLA-Tencor) Proper endpoint control of the polishing process on the metal/dielectric layers is critical for copper CMP — poor copper endpoint control causes yield loss. If too much material is removed (overpolishing), metal dishing or oxide erosion can occur, which leads to copper pooling and photolithography problems. Removal of too little material (underpolishing) can result in residual copper and incomplete removal of the barrier layer, leading to metal shorts. Endpoint detection requires that several factors be considered. Underpolish or overpolish process window parameters must be clearly defined. How critical is the time when copper starts clearing, and when is copper removal complete? How critical is the time from starting to clear the dielectric barrier to the end of polish? What are the endpoint performance specifications? The importance of measuring metal pre- and post-polish, as well as measuring dielectric post-polish, must be established. Determining the number of copper CMP steps per process is another important consideration. Before the development of in situ metrology, where a sensor is embedded into the CMP tool to take film thickness and uniformity measurements, wafers had to be taken to an off-line metrology tool to detect film variances in order to adjust the CMP process accordingly. An essential component of advanced CMP equipment today is the use of in situ endpoint technology that precisely determines the exact point during polishing at which the copper film is completely removed from the entire wafer surface without damaging the underlying layers. Current "optical only" and "eddy-current" in situ methods provide limited information that CMP engineers need to optimize their copper CMP processes. Several issues limit the effectiveness of optical-only methods. Optical endpoint systems in use today are plagued with previous level pattern noise when polishing upper metal layers. They also cannot provide real-time removal rate and uniformity measurements. Most commonly used eddy-current methods can provide only relative film thickness measurements. CMP process engineers are notified only when they have reached a new layer, by which time it may be too late to stop the polishing process without removing some of the material on the next layer — which leads to dishing or erosion. A combination of single-wavelength, multi-angle optics and eddy-current measurement techniques can provide an optimum CMP process control solution. Measurement of impedance vectors (both in-phase and quadrature) by an eddy-current probe can provide absolute thickness measurements vs. scalar measurements. Using an eddy-current probe, manufacturers choosing to rapidly polish the bulk thickness of copper first can now stop at an accurate thickness. After a change in process conditions, they may then proceed to a second polishing step and completely remove the copper film over the entire wafer. The eddy-current technology's ability to provide an absolute thickness profile across the entire wafer in real time will enable customers to monitor the copper film's planarity during removal. On-the-fly compensation techniques can eliminate the impact of pad temperature and pad wear during the CMP process, without which false measurements could occur. A single-wavelength laser — as opposed to a multiple-wavelength approach — can minimize noise from slurries and reduce the incidence of false measurements. Reporting of false end points, a fatal error in volume production, can be eliminated with the use of a multi-angle reflectometer. In addition, multilayer film stacks need the comprehensive data provided by a multi-angle laser reflectometer in the optical probe. The combination of optical and eddy-current technologies allows chipmakers to monitor the copper CMP process from start to finish. Multiple steps within the CMP process can be run with a high degree of repeatability for each step. CMP process repeatability and throughput can be improved simultaneously.

Victoria Shannon is vice president of technology, integration and applications, at Novellus Systems. She holds a Ph.D. in physical chemistry from the University of California at Berkeley.

David C. Smith is vice president and general manager of the Electrofill Products Division of Novellus Systems. He holds a Ph.D. in inorganic chemistry from the California Institute of Technology.

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REFERENCES

1. T. Oshima et al, IEEE IEDM Tech. Dig., 2000, p. 123.
   
2. G.B. Alers et al, IEEE International Rel. Physics Symp., 2001 (in press).
   

Acknowledgements

The authors wish to acknowledge the work of the following colleagues from Novellus Systems Inc., upon which much of this discussion was based: Jon Reid, Steve Mayer, Ted Cacouris, Glenn Alers, Kirthi Kattige, Lap Tam, Eliot Broadbent and Gary Ray, as well as the staff of the Customer Integration Center. The authors would also like to thank Gary Ray, Glenn Alers and Patrice Geraghty for reading this manuscript, and for their helpful comments and additions.