Industry Divides on Low-k Dielectric Choices

		At a Glance
	At the 0.13 µm node, device manufacturers are split among those that will use an organic spin-on dielectric (SOD); those that will use silicate films, produced by PECVD or SOD; and those that will wait until future generations to use these new films. The ability to overcome extensive integration challenges and extend a material's performance will determine a company's long-term success at attaining a low effective dielectric constant (keff). Together with copper interconnects, low-k dielectrics deliver faster device speed and reduced crosstalk in advanced devices.

Like the political divide in the latest U.S. presidential election, the semiconductor industry is split when it comes to identifying the best low-k dielectric material. With the notable exception of Intel, several device manufacturers, including AMD, Motorola, IBM, Infineon, TSMC and UMC, have announced intentions to use low-k materials at the 0.13 µm generation.¹ This move is the culmination of many years of hard work. Since 1994, International SEMATECH (ISMT, Austin, Texas) alone has invested tens of millions of dollars with suppliers, universities and internally to determine the best low-k interlevel dielectric, according to Jeff Wetzel, Motorola assignee and low-k program manager at ISMT. "The challenges have proven to be substantial, requiring new approaches for characterization and integration of low-k materials with copper," he said.

The low-k market is split between an organic spin-on dielectric (SOD) film and hybrid organic/inorganic silicate films made by CVD or spin-on processes. Bob Miller, manager of advanced organic materials at IBM's Almaden Research Center (San Jose), summarizes the two categories of dielectrics: "The silicate films are extremely thermally stable and reasonably hard, but they are fragile materials. Organic materials have reasonable thermal stability and are tough, but they're soft. Each has advantages and disadvantages."

The fundamental material limitations of all low-k dielectrics have led to serious integration challenges, including resist poisoning, adhesion issues brought out by CMP, and substantial changes in processing (Table 1). "Many of the baseline processes that were available and straightforward for oxides are definitely not straightforward for low-k dielectrics," said Karen Maex, strategic research coordinator, Si Processing Technology Division, Interconnect Technologies and Silicides at IMEC (Leuven, Belgium). "The patterning and integration schemes are very different, and the resist stripping process has become a science rather than a routine clean-up step as it was for oxides. So you have to start from scratch in many details of the process."

For next-generation ultralow-k(k<2.2) dielectric materials (k_eff=2.5), device manufacturers will transfer learning from the k=2.7 films to the 2.2-2.0 films. So while the transition is expected to be fairly straightforward, in most cases going from a dense material to the same material with porosity added, device manufacturers will be integrating porous films for the first time in semiconductor manufacturing history. Researchers are tackling tough questions regarding the behavior of porous films, ways of generating and controlling porosity, attaining a sufficiently small pore size, and ways of testing the strength of these soft or brittle films.

Timing and roadmaps

	The performance of spin-on low-k dielectrics is typically extended by adding porosity to an existing material to lower k eff of the ILD stack. (Source: Dow Corning)

When Semiconductor International began its wider coverage of low-k dielectric technology three years ago,² there was little consensus on the material of choice or the optimal integration scheme. Some companies were integrating low-k dielectrics with aluminum interconnects, but the majority of device manufacturers were waiting to first implement copper damascene interconnects with SiO₂ or FSG ILD, stalling the switch to low-k dielectrics. Some things have not changed.

What has changed is the process viability and integration knowledge gained by having hundreds of engineers and researchers working with ILD materials that are less dense than SiO₂, less reproducible than SiO₂ and not nearly as thermally or mechanically stable as SiO₂. Since last year, CVD of organosilicate glass (OSG) films have matured to the point where films with k ranging from 2.6 to 3.1 are being integrated into 0.13 µm devices, and suppliers are claiming the feasibility of CVD films down to k=2.15. This progress follows on the heels of spin-on solutions that have demonstrated extendability to 2.0. One advantage to SODs is the consistency of k value, with predefined chemistry, which may make for a more reproducible k value compared with CVD films.

Table 1. Technical Challenges for Low-k Integration
Deposition	Silicate-based CVD +Film stability +High throughput +Existing equipment +No need for hard mask layer -Process incomplete (new chemistries to be implemented)	Silicate-based SOD Organic SOD +Process easy to implement +Good planarization +No need for ARC (HM can be tuned to act as ARC) -Tools to be purchased
Etch	+Well understood etching chemistries -Low selectivity between hard masks and dielectrics	+Good dielectric/HM selectivity +Reduced clean of etch chamber (increase throughput) -Profile/bowing effect
Cleaning	+Dry and wet chemistries well understood -Needs to be Cu compatible -Risk of CD loss -Irreversible deformation/swellingincreases with porosity	+Very resistant to chemistries -New cleaning chemistries to be investigated -Risk of delamination between organic dielectric and HM film -Profile/bowing issue with dry cleaning
Source: CEA-LETI

 

CVD OSG films are available from Applied Materials (Santa Clara, Calif.), with its Black Diamond I and II films, delivering k of 3.1 to below 2.4; Novellus Systems (San Jose), with CORAL films at the 2.7-2.8 and 2.2-2.4 levels; Trikon Technologies (Newport, UK), with its Flowfill CVD at 2.8 and PECVD solutions at a k of 2.2, measured at ISMT; and ASM International (ASMI, Bilthoven, Netherlands), which provides k=2.7 and below CVD solutions.

In the spin-on realm, key players include Dow Chemical (Midland, Mich.), maker of SiLK SOD (k=2.65); Dow Corning (Midland, Mich.), provider of FOx HSQ material (2.9) and XLK (2.0) porous HSQ material; JSR, provider of MSQ at 2.7 and two porous films at k=2.0-2.2; Air Products through its Schumacher unit (Carlsbad, Calif.), maker of MesoELK (2.2); Honeywell Electronic Materials (Sunnyvale, Calif.), provider of Nanoglass 2.0 material, GX-3 and HOSP films; and TOK (Tokyo). (For more information on these films, see "Designing Porous Low-k Dielectrics,".) In addition to providing spin-on solutions, Dow Corning and Air Products/Schumacher provide low-k CVD precursors including trimethylsilane, tetramethylsilane, tetramethylcyclotetrasiloxane (TOMCATS), silicon tetrafluoride and others.

Extendability of material is the primary consideration in selection. Miller explained IBM's choice of SiLK SOD from Dow Chemical: "When this program began, we were most interested in the spin-on materials because it was clear that those materials were more likely to be extendible to k of 2.2 and below."

In efforts to extend CVD OSG films below k=2.6, some equipment suppliers are exploring different chemistries. "We have evaluated a very large group of organic precursors, and many of these precursors allowed us to make films down to only 2.6," explained Wilbert van den Hoek of Novellus. "About four months ago, we found a new class of precursors that enable us to decrease the k value of the PECVD SiOC film to the 2.2-2.4 range," said van den Hoek (see "Precursor Selection for PECVD Low-k Films").

Because of competitive pressures, the timeline for low-k implementation is accelerating. "Companies are constantly trading off between stretching the design with the old materials or staying with a proven design and pushing it with a new material," explained Mark Loboda of Dow Corning. "Sooner or later, engineers need to make measurements on real devices and, based on that data, make the low-k choice that best meets their needs. If they could do that for the 2.7 films, it would become very apparent what will be needed for the next generation."

All in the integration

To handle the various integration obstacles, device manufacturers are likely to use hybrid or embedded structures — using low-k materials between the copper wires, where they are needed most, and using denser FSG or SiO₂ at the via levels, to stabilize the structure and improve thermal stability. In addition, the upper levels of metal benefit less from the low-k material, so a harder film can be used to further prepare the overall device structure for assembly and packaging operations (Fig. 1). These changes are forcing companies to reevaluate probing, wafer dicing, die bonding and wire bonding materials and procedures.

Perhaps the most significant integration challenge for low-k materials is resist poisoning, caused by the reaction of amine-based byproducts with chemically amplified photoresist, which prevents resist dissolution during the development step. Resist poisoning can be brought about by plasma sources that convert nitrogen or ammonia gases to atomic nitrogen that quickly react with hydrogen and diffuse into the low-k films, van den Hoek explained. The gas is later released from the film, and it interacts with the exposed photoresist layer.

	1. Process integration includes the consideration of the impact of assembly and packaging processes on the overall device structure. (Source: International SEMATECH)
	2. Via-first processing challenges include the need to fully remove photoresist in the via, a long trench etch, potential interaction between the resist and low-k material, and a need for damage-free stripping. (Source: International SEMATECH)
	3. Dual-damascene dense metal structure of M2 on M1 using Aurora 2.7 CVD process for a 0.13 µm technology node. (Source: IMEC)

Susan Vitkavage, technical manager of the Interconnect Group at Agere Systems (formerly the Microlectronics Group of Lucent Technologies in Allentown, Pa.), emphasized the seriousness of the problem. "Resist poisoning has a fundamental impact on your process and can actually dictate the way you choose your integration scheme," she said. "You can sometimes get around the poisoning by choosing a different integration scheme, but you will pay a penalty in terms of overlay tolerance and therefore packing density. Thus, resist poisoning is not just a problem because of the chemical interactions; it's a fundamental design rule and packing density problem."

Resist poisoning must be addressed throughout the process. Commonly, a hard mask or dual hard mask can be used to prevent direct contact between the DUV resist material and the low-k dielectric, but this may not be sufficient. "There is no magic bullet," said Ken Monnig, associate director of interconnect at ISMT. Even in cases where ammonia is used during the curing process of an SOD, he added, "you cannot categorically say the film is going to pose a problem from the standpoint of resist poisoning." Monnig warned that, as the industry begins its transition from 248 nm to 193 nm formulations, the new resists are expected to be even more sensitive to amine-based poisoning.

Successful process integration also requires optimized etching and stripping procedures, especially in a via-first integration scheme, the most commonly used scheme today (Fig. 2). Depending on the low-k film, different etch stop, capping and antireflective coating layers can be used. Recent attempts to eliminate the intermediate etch stop layer between trench and via put further strain on a "timed etch."

Although low-k etch processing does not display fundamental etch problems, the films must be optimized for high selectivity and complete removal of residue in etched vias and trenches, explained Steve Lassig, senior manager of process integration at Lam Research Corp. (Fremont, Calif.). "With OSGs and SiC films, we're starting to approach the etch selectivities we achieved with FSG and nitride, which is greater than 20:1," he said.

As in other areas of etch processing, the vendors are offering integrated etch, in situ strip and surface conditioning processes, which prepare the surface for metal barrier layer deposition. According to Lassig, this integrated approach provides technical and CoO advantages. "Because of the integration requirements, we have become much more cognizant of the etch chemistries we're using because the chemistry may affect the surface quality, which can have a bearing on the adhesion of the barrier layer," he said.

The reason copper CMP over low-k dielectrics is such a challenge begins with the softer, more fragile nature of the materials. Much emphasis has been put on determining a hardness or Young's modulus threshold that corresponds with a material's ability to endure CMP and wire bonding processes. "With regard to CMP, we do see a correlation between hardness and the film's ability to withstand polishing, but it's not as clear as we would like," Monnig explained. "It's not just modulus or toughness, but more likely a combination of the two that are needed to specify potential success of these materials in a given integration."

Agere's Vitkavage said, "There appears to be a correlation between Young's modulus and mechanical performance, somewhere around 5 GPa. However, we have experienced failures during CMP even when the adhesion numbers looked fine, so you really have to look at the failure mode, which can be adhesive or cohesive. We're still searching for a good way of modeling CMP failures."

But in dual-damascene processing, there are larger implications associated with the CMP process's control over metal area. "The switch from aluminum to copper really created a shift. With aluminum, we only worried about linewidth control because we always had good control of the thickness of the metal we deposited," explained Vitkavage. "For copper processing, plasma deposition does a pretty good job of hitting the target of trench depth, and lithography can define the width of the trench, but the final metal thickness, which used to be very controllable, is now controlled by CMP, the weakest link in the chain."

Regarding the polishing of ultralow-k films(k<2.2), Novellus's van den Hoek asserted, "CMP is going to be a huge issue going forward." In fact, CMP solutions that currently deal with the issues of copper dishing and erosion of barrier films will only become more significant concerns on softer low-k materials and 300 mm wafers. Figure 3 and Figure 4 show dual-damascene copper structures with ASMI's Aurora 2.7 process and SiLK dielectric, respectively.

Thermal stability also appears to be an issue, especially in multilayer metal stacks where the lower levels of ILD must undergo several copper annealing steps. Users demand materials with stability typically to 425°C.

Etch stops and hard masks

The silver lining in this low-k feat is the development of silicon carbide-based films that can replace nitride films (k=7-9) and function as capping layers, hard mask or etch stops together with the low-k films to deliver a lower k_eff stack. Several years ago, Dow Corning's Loboda pioneered the development of SiC-based films based on the company's trimethylsilane, which also can be used to form SiOC films. SiC-based films with terminating hydrogen are offered by Applied Materials, Novellus, Trikon and ASMI, and deliver k values of 4.3-4.8. "You can almost gain as much benefit in effective k value by changing from a nitride to a carbide on a 2.7 material as you would get by keeping the nitride film and integrating it with a k=2.0 dielectric," IMEC's Maex said.

	4. Dual-damascene via chain in spin-on dielectric for the 0.13 µm technology node. (Source: IMEC)

SiC must be optimized for low leakage current. It is not good enough to develop a SiC film with low leakage at room temperature. For instance, microprocessors operate at ~80°C and at this temperature, leakage can be an order of magnitude higher if the SiC is not properly passivated, according to van den Hoek. "The silicon carbide films are still fairly recent and they still need some process maturity," Vitkavage said, adding that device manufacturers are having different levels of success with the different commercial films.

Applied Materials' low-k copper diffusion barrier, etch stop and hard mask (BLOk) has been successfully integrated with FSG, Black Diamond and SOD films. It uses the same precursor as Black Diamond as well as the same chamber. "BLOk works well in terms of adhesion, integrity of the film and the ability to withstand CMP condition," said Applied's Farhad Moghadam. "SiC films have proven to provide significant advantages over SiN. Not only does it provide a lower effective k for the damascene stack, but it enables greater adhesion to SiOC and can act as a CMP stop for SOD." For higher throughput and better interface characteristics between the low-k and SiC films, Applied is getting many requests to integrate these processes in the same chamber. "A universal chamber provides throughput advantages with greater process flexibility and manufacturability," said Moghadam.

Ironically, SiC films are proving to be more enabling when integrated with organic spin-on low-k films than CVD films because of greater etch selectivity between organic SOD and SiC relative to OSGs and SiC. Though it is unclear whether the industry will even get there, spin-on users are driving toward all spin-on solutions. Honeywell and Dow Chemical are developing low-k hard mask and etch stop films. Dow Chemical's Mark McClear said the company expects to introduce a hard mask and etch stop film with a k of 3.1 at SEMICON West this year. Honeywell's Mike Thomas said his company will soon introduce a high glass-transition-temperature silicate-based film with a k of 2.6, which can be used with its HOSP dielectric or Nanoglass porous silica film to deliver k_eff in the 2.0 regime. Thomas added that, by manipulating the barrier metal that binds to the low-k film, some films that did not work in production previously, because of insufficient hardness, may be made manufacturable.

Next-generation materials

Research programs at IMEC and ISMT have been instrumental in characterizing and understanding the behavior of next-generation porous films with a k in the range of 2.4-2.0, (Table 2). "For the lower values, 2.4 and below, I think there is a lot of designing of the material to be done," Maex said.

Two unavoidable consequences result from the reduction in k value: The films are not as hard, with implications for CMP and wire bonding, and their thermal conductivity is significantly lower than that of SiO₂. "The same type of technology that you use to promote reliability in fragile materials, like dummy vias, can also help with thermal conductivity," IBM's Miller said.

With ultralow-k materials, many of the integration issues — such as adhesion problems and resist poisoning — become more serious with the lower-density, more porous nature of the films. "For instance, in a via-first integration scheme, when you etch an ultralow-k CVD film, during the trench etch you need to prevent resist and chemicals from penetrating the sidewall of the via," Moghadam said. Trikon's Andy Noakes asserted that the reduced hardness of these materials will encourage their use with films of increasing k value as you go up the stack to ease integration.

Initial findings at IMEC indicate that smaller pore size for the same porosity is preferred, and attaining and maintaining pore size throughout processing is advantageous. However, as with the initial 2.7 materials, maintaining a stable k value is quite a challenge. "The 2.7 generation may be with us longer than we think because, at the moment, a lot of the dielectric materials in the 2.2-2.4 range as deposited do not stay at 2.2 or 2.4 after processing. They are closer to 2.7," Vitkavage said.

ISMT's Monnig agreed that, while many of the ultralow-k films do not maintain their k values throughout processing, recent research shows one spin-on material that is capable of maintaining its 2.0 k value. "We are now much more optimistic than we were three months ago when no material was showing this promise," he said. ISMT now needs to investigate how extendible this new film is and how it performs upon device integration.

Research at IBM indicates there is a maximum amount of porosity that can be put into a material and still maintain a closed-cell structure. "Depending on what you're using for a sacrificial porogen, the structure of the resin and the process, our experiments suggest that above a 20-30% porous film can deliver a film with a dielectric constant of 2.0 to 2.2 if you have the right material, but 30% may be the limit for closed cell," Miller said.

He explained that, although a closed-cell approach is preferred, it may be difficult to get all the desired film properties with porous films that are closed. "Any other technique, like chemically induced phase separations, for instance, will deliver an open-cell structure." In fact, ultralow-k materials with open-cell structure (all pores are interconnected) have undergone the most rigorous evaluations at ISMT.

With porous ultralow-k materials, Maex emphasized, "Integrity of the barrier on a porous sidewall is important, and has not been addressed sufficiently. We don't know which pore structure is best, nor do we know the best way of achieving a porous structure. But there are a lot of new materials coming up with very interesting characteristics."

From a metrology standpoint, much work on characterization and process control is also needed to control pore size, connectivity of pores and pore density. Currently, analytical tools such as positron annihilation lifetime spectroscopy or small-angle neutron scattering are used off-line, but throughput is insufficient for use in a fab environment.

The industry does not have a good tool for determining pore size distribution, Monnig said. "What we would like to know, among all the pores throughout the film, literally billions upon billions of pores, is whether there is one or more pore that is greater in size than one-tenth of the feature size, for instance. But we don't have any way of gaining that information, even with a lab full of giant analytical tools."

Conclusions

The industry is gradually adopting low-k dielectric materials, some companies at the 0.13 µm technology node, others at 0.10 µm or beyond. It appears that the current-generation 2.7 materials will keep engineers busy in the near term, though a vast expanse of learning will be required to integrate and adopt porous dielectrics.

Precursor Selection for PECVD Low-k Films Paul Brunemeier, Ph.D., senior manager, strategic technology, Novellus Systems, San Jose 1. Several CVD films hit a lower limit of k~2.7. The many benefits driving device manufacturers to use low-k dielectric materials include increased device speed, reduced power and heat dissipation requirements, and reduced interline crosstalk. However, the transition to these materials has been delayed primarily because of challenges in their integration, including etch and stripping problems associated with the carbon content in the materials.1 For a given k value, a key challenge is to produce a film with adequate hardness for undergoing CMP and various assembly and packaging steps. Based on the evaluation of several families of precursors, we have determined that PECVD precursor selection has a large impact on the film's carbon content and hardness, both of which can be optimized for ease of integration. In contrast to SiO2 deposition, where TEOS has been chosen as the preferred organosilane precursor, there are many precursors to choose from for low-k dielectrics. Mark Loboda of Dow Corning pioneered the use of trimethylsilane for depositing organosilicate films.2 For alkylsilane-based precursors, as well as for a novel silicon-containing organic precursor (Fig. 1), dielectric constant decreases with carbon concentration (as FTIR peak ratio). There is a pronounced, repeatable lower limit on k as carbon concentration is increased beyond a critical value, such that incorporating more carbon in the film has no k-reduction benefit. Films made with the 3MS and 4MS bear very similar characteristics across the range of carbon concentration. Understanding the relationship between the precursor and resulting film properties allowed us to identify a new, novel silicon-containing organic precursor. 2. A new organic precursor allows simultaneous optimization of hardness and carbon content. Exploration of a variety of process conditions has led to a range of hardness values measured for films of a given carbon concentration (Fig. 2). There is also a clear trend of decreasing hardness with increasing carbon content in the film. The novel precursor has allowed us to achieve a minimum k value at a significantly lower carbon concentration in comparison with the alkylsilane family of precursors (see arrows in Figs. 1 and 2). We were able to attain a dramatically harder film with this novel precursor while maintaining a minimal k value of ~2.8. Based on additional learning from this second group of precursors, we developed a fundamental understanding of the relationship between precursor characteristics and film properties, and were able, again, to identify a new class of precursors that allow k values of 2.2-2.4. These values have been achieved without resorting to creation of physical pores in the material, but instead employ steric hindrance associated with the organic group attached to the Si-O network. It is worthwhile to note that the films in this range have a hardness equivalent to that of SOD with k<2.7. REFERENCES G. Ray, "Low-k Dielectric Integration Challenges," American Vacuum Society, 2nd Annual ICMI Conf., February 2000. M.J. Loboda, "New Solutions for Intermetal Dielectrics Using Trimethylsilane-Based PECVD Processes," Microelectronics Engineering , Vol. 50, 2000.

For more information Applied Materials ASM International Clariant Corp., AZ Electronic Materials Dow Chemical Dow Corning Honeywell Electronic Materials JSR Novellus Schumacher Shipley Co. TOK Trikon Technologies

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REFERENCES

1. L. Peters, "Low-k Dielectrics Get Respectable," Semiconductor International, April 2001.
   
2. L. Peters, "Pursuing the Perfect Low-k Dielectric," Semiconductor International, September 1998.