Low-k Dielectrics Get Respectable

The integration issues and reliability concerns that have prevented low-k dielectrics from entering the production environment for two technology generations are finally being overcome. Major device manufacturers are weighing in with their dielectric of choice for the 0.13 µm generation, splitting the market among at least four materials from four suppliers, including CVD and spin-on dielectric solutions. And the battle is not over yet.

Although each of these approaches target copper/ low-k interconnect structures, the low-k market is not limited to high-speed multilevel logic devices. For more than a year, Trikon Technologies (Newport, UK) has provided a low-k Flowfill solution to LSI Logic for subtractive aluminum schemes, and it recently won the business of a leading producer of memory devices.

Companies such as Intel, NEC, Fujitsu, Philips, Lucent Technologies, Hyundai and Chartered Semiconductor have yet to publicly commit to a low-k material choice.

The integration issues for low-k films are largely the result of trying to find a low-k dielectric film with electrical, thermal and mechanical properties comparable to those of SiO₂ (k=3.9-4.3). Important metrics include film hardness, film strength (modulus), film stability throughout processing, glass transition temperature, and low k_eff. A low k_eff represents the "holy grail" of the intermetal dielectric stack, largely determining the line-to-line capacitive coupling and RC delay of the interconnect, the very reasons for adopting a low-k material in the first place.

A viable low-k material must be compatible with dual-damascene lithography, etching, stripping and cleaning processes, and especially polishing (CMP) and device packaging (including wire bonding) methods. Additional films, including etch stop layers, hard masks (for patterning assistance) and capping layers (to protect the low-k film during CMP) strongly influence k_eff. Early integrators of low-k films, which today offer k_eff values of about 3.0, encountered an insidious problem of photoresist poisoning, which required fundamental and empirical research to solve.

The reliability of devices containing multilayer dual-damascene stacks is related to several factors including adhesion of the barrier metal (typically Ta/TaN stack) to the low-k film; adhesion of etch stop, hard mask and capping layers to the low-k film and barriers; and the ability to polish the copper and package the device without pattern shift.

"CMP exposes your stack to high shear forces, so any weakness at the interfaces, which may not show up immediately, could lead to long-term reliability problems," explained Farhad Moghadam of Applied Materials. He also talked about the importance of consistent trench depth, a challenge made more difficult by the desired elimination of intermediate etch stop layers between the trench and via, requiring a production-worthy timed etch. Other factors affecting device reliability are thermal budget and dielectric compatibility with higher-temperature(>400°C) copper annealing.

The low-k launch

Even with this recent flourish of announcements, the low-k battle is far from over (check out a feature article on low-k dielectrics in next month's SI). DRAM devices, which account for about a third of the wafers processed today, will not require low-k material performance perhaps until the 0.07 µm generation. Companies also will delay copper/ low-k dielectric use until costs and yields become comparable to those of SiO₂/Al interconnects.
— Laura Peters

Joint Project to Develop "Supercomputer-on-a-Chip"

Sony Computer Entertainment Inc. (SCEI, Tokyo), IBM Corp. (White Plains, N.Y.) and Toshiba Corp. (Tokyo) announced plans to research and develop an advanced chip architecture for a new wave of devices in the emerging broadband era. The companies will collectively invest more than $400M in the next five years to design a "supercomputer-on-a-chip."

Under the agreement, the three companies will establish a joint development center within an IBM facility in Austin, Texas. At its peak, the center will be staffed with nearly 300 computer architects and chip designers dedicated to the development project.

Code-named "Cell," the new microchips will employ the world's most advanced research technologies and chipmaking techniques, including copper wires, silicon-on-insulator (SOI) transistors and low-k dielectric insulation, with features smaller than 0.10 µm.

The result will be consumer devices that are more powerful than IBM's Deep Blue supercomputer, operate at low power and access the broadband Internet at ultrahigh speeds. Cell will be designed to deliver "teraflops" of processing power.

Under the agreement, SCEI, IBM and Toshiba will each manufacture the product for a variety of consumer applications.

"The processor platform that people have only been able to imagine is now going to become a reality," said Ken Kutaragi, president and CEO of SCEI. "The new broadband processor, code-named Cell, that we are going to create, will raise the curtain on a new era in high-speed, network-based computing. With built-in broadband connectivity, microprocessors that currently exist as individual islands will be more closely linked, making a network of systems act more as one, unified 'supersystem.' Just as biological cells in the body unite to form complete physical systems, Cell-based electronic products of all types will form the building blocks of larger systems. SCEI, IBM and Toshiba are mapping out the future of broadband computing."

"We're defining the next era of computing, providing the technology that will bring computer intelligence and network access to a wide array of consumer electronics," said John Kelly, senior vice president and group executive for the IBM Technology Group. "As a result, IBM's advanced chip technologies are in more demand than ever. We expect a considerable portion of our new, state-of-the-art 300 mm wafer manufacturing facility in Fishkill, N.Y., to be dedicated to this product."
— Peter Singer

Infineon Uses SiC to Make Power Schottky Diodes

Infineon Technologies (Munich, Germany) has made power semiconductors based on silicon carbide (SiC), offering significantly lower switching losses and higher switching frequencies than conventional silicon or gallium arsenide power diodes. They can also provide higher operating voltage ranges than the limited values offered by silicon Schottky devices. The low losses of the SiC components enable compact switched-mode power supplies (SMPS) to be designed using high switching frequencies without the need for complex resonant switching circuits or snubbers.

According to the company, SiC is the ideal material for power semiconductor products that must have a high blocking voltage because it has a high Schottky barrier voltage, a very high electrical breakdown field strength and a thermal conductivity comparable with that of copper. These characteristics result in low leakage currents, low on-resistance and high current densities. While silicon Schottky diodes can provide blocking voltages of only ~200 V and GaAs Schottky diodes up to 250 V, SiC Schottky diodes can offer values of 300-3500 V.

The low switching losses allow SMPS circuits to be designed without heatsinks or fans, reducing system costs. Further savings can be achieved through the use of smaller and fewer passive components and smaller, more cost-effective transistors because of the lower switching currents, higher switching frequencies and lower losses in circuits using SiC diodes.

"An essential advantage of Infineon's SiC technology is that it makes possible almost loss-free and very fast switching diodes," said Reinhard Ploss, senior vice president and general manager of Infineon's Automotive and Industrial Business group.
— Brian Dance