The New Packaging Driver: Network Application Chips
Eric Bogatin, Contributing Editor -- Semiconductor International, 4/1/2001
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Last year, AMD announced the introduction of an Athelon processor running at 1 GHz. This was quickly followed by Intel and IBM announcing processor clocks in excess of 1 GHz. These frequencies are close to the starting place for chips used in networking applications.
One measure of the clock rates used in network applications is the Optical Carrier (OC) designation, used in SONET-based systems.
In a typical two-voltage-level modulated system, the bit rate is the clock frequency. However, in multilevel modulated systems, the clock frequency may be less than the bit rate.
For gigahertz applications, "... the electrical effects are the No. 1 concern, above and beyond any mechanical or thermal issues," said Bill Beale, packaging engineer with Accelerant Networks (Beaverton, Ore.), a provider of high-speed transceiver chips. "We can't even choose a package unless we model and simulate it first."
In its low-pin-count (140 pins) application, flip chip was required to minimize the package parasitics. "At speed, the wire bonds would have had poor performance," Beale said. But careful routing of differential pairs allowed the use of a low-cost, two-layer organic BGA.
Though the latest 136 × 137 OC-48 crosspoint switch from Conexant also uses a flip-chip BiCMOS chip on a co-fired ceramic ball array package, wire bonding is not dead.
"Wire bonds have plenty of juice for OC-48," said Hassan Hashemi, director of product development for the Advanced Packaging Group at Conexant (Newport Beach, Calif.). The caveat, he added, is that they must be designed right.
For example, wires of differential signal pairs need to be kept very close together, with short, straight wires. A wire bond-based package can have better signal integrity because the signal routing does not have to flow through a redistribution layer as it would if flip chip were used. For the next-generation OC-768 chips, wire bonds might be a requirement if GaAs chips are used because there is currently no flip-chip process for GaAs that is suitable for large die in volume production.
Figure illustrates the resonant mode of a 35 mm body size package. At this body size, the package resonance is just about the OC-48 frequency. This could cause disastrous crosstalk and EMI. Every network application will have to deal with — and design out — package resonances' effects.
"We implement automatic design rule checking to prevent any physical lengths to be resonant at the OC-48 clock," Hashemi said.
"Early simulations showed a big resonance at 2.5 GHz in a BGA with an internal plane," Beale explained. "We avoided this problem by going with tightly coupled differential pairs and no plane."
In this new regime of extreme performance packages, everyone agrees that one of the keys to successfully implementing a new package design is choosing good electrical design rules and leveraging accurate electrical modeling and simulation. The earlier this is performed in the design cycle, the greater the chance of first article success. This means faster time to market and lower development costs.
Eric Bogatin, chief technical officer at GigaTest Labs (Sunnyvale, Calif.), has worked in the high-speed packaging and interconnect field for more than 20 years. He received his B.S. and Ph.D, both in physics, from the Massachusetts Institute of Technology (MIT, Cambridge) and the University of Arizona (Tucson), respectively.
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