Calibrating CD Metrology Tools to 1 nm
Laura Peters, Senior Editor -- Semiconductor International, 4/1/2001
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The approach uses electrical voltage-contrast CD measurements, which are then calibrating using high-resolution TEM (HRTEM) measurements, taking advantage of the known separation of lattice planes in single-crystal silicon. The group demonstrated a path for providing low-cost CD reference features with a total uncertainty as low as 0.9 nm. The work was reported in the February issue of IEEE Transactions on Semiconductor Manufacturing.
The NIST/Sandia researchers fabricated a 10 mm square test chip patterned in a BESOI (bonded-and-etched-back silicon-on-insulator) substrate. They produced reference features down to 100 nm in monocrystalline silicon with all feature edges aligned to specific crystal planes. The buried SiO2 layer was produced thermally before bonding, creating a sharp interface between silicon and oxide. The reference features have {110} top and bottom surfaces and edges aligned to the {111} planes along <112> directions.
Reference feature widths must be at or below the widths of the smallest CD in production, so this material was built with a range of features down to 100 nm. Because HRTEM is a destructive method, the group recommends its limited use on a small number of reference features, performed only after electrical probe.
To measure electrical CDs, the group used a short bridge resistor variant of the common cross-bridge resistor. The cross-bridge resistor combines a van der Pauw cross with three reference features and bridge resistors. The researchers measured sheet resistance of the conductor by measuring two complementary, four-terminal resistances of the cross structure. The electrical length is the physical length, corrected to compensate for the presence of non-zero width voltage contacts.
The secondary calibration, using HRTEM, provides the width of the sample as a count of silicon lattice fringes that run parallel to the sidewalls of the reference feature. To resolve lattice atomic fringes, the sample dimension was reduced to 20 nm, using TEOS film deposition, polishing and argon milling. From the TEM image, the group developed a procedure to digitize the 83 × 102 mm negative at 3000 dpi and then count the fringes using image processing techniques.
The group's uncertainty estimation for HRTEM measurements (Table) considered uncertainties in determining the lattice plane count (1.25 nm), the value of the silicon lattice fringe spacing (9 × 10-9 nm/fringe), and uncertainty in the silicon lattice constant due to arsenic doping (2.14 × 10-6 nm) and thermal expansion (2.78 × 10-6 nm). Because there were 1859 fringes in the sample, the uncertainty in width measurement due to uncertainty in the lattice constant was 0.004 nm. The total HRTEM uncertainty was 2.5 nm.
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Table. Uncertainties of Different Width Measurements |
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| Calibration step | Uncertainty source | Uncertainty value, s i (nm) |
| Primary: High-resolution TEM | Lattice count: fringe
count at edges Silicon lattice constant: Uncertainty in a Doping Temperature (±2K) Combined uncertainty (one fringe) Combined uncertainty (1859 fringes) Combined standard uncertainty, 2=Ö S si2 |
1.25 9×10-9 2.14×10-6 2.78×10-6 3.51×10-6 0.004 2.50 |
| Secondary: Electrical CD |
Sheet
resistance Bridge resistance Length (unmeasured) Combined standard uncertainty, 2=Ö S si2 Length (measured) Combined standard uncertainty, 2=Ö S si2 |
0.18 0.06 2.5 5.0 0.4 5.0 |
The electrical CD measurement uncertainty considered the length of the bridges and random variations in voltage and current in electrical measurements. Using a worst-case 600 nm feature, uncertainty in bridge length was 1% or 2.5 nm. But when the NIST Linescale Interferometer was used to measure random variation in length, the result was 0.4 nm. For van der Pauw measurements, the random variation was 0.03%. For bridge resistances, the result was <0.01%. When the bridge length is known, total uncertainty in electrical measurements is 0.9 nm, and 5.0 nm when the length is not known.
For additional information on yield management, go to www.semiconductor.net/yield
