MEMS Demand New Package Designs
Tai-Ran Hsu, San Jose State University, California -- Semiconductor International, 4/1/2001
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Electromechanical packaging is a critical factor in commercializing microsystems. For example, the cost of packaging micro pressure sensors can vary from 20% to 95% of the product's total cost. Often, the size of a micromachined sensor is dwarfed by the size of its final package.2 A sensing or actuating element of a few microns can end up in a package with an overall size in centimeters. Consequently, most of the benefits of miniaturization are diminished because of inadequate packaging. The high cost and the undesirable bulky packages have been major stumbling blocks in capitalizing the market potential of micro engineering products.
The lack of electromechanical packaging standards and design methodology is the principal reason for the inadequate packaging of microsystems. There are several reasons for this. One is the late participation of mechanical engineers in developing MEMS technology. Consequently, the mechanical design aspect of microsystem products often was overlooked, and much effort has been concentrated on the fabrication processes and utilization of existing materials traditionally used in microelectronics. Another reason for this unfortunate lag is that the microsystems and MEMS industry is regarded as a high-risk, high-pay-off industry. As such, much information related to the product design and packaging is treated as well-guarded commercial proprietary secrets. Companies are not willing to disclose the details of their fabrication processes, the material properties they used, or the engineering design and packaging processes they followed. This reluctance in sharing knowledge and experience actually has retarded the potentially rapid advancement in microsystems product development.
Microelectronics and microsystems packaging
Many would agree that much of the MEMS and microsystems technologies evolved from microelectronics. As such, most microfabrication techniques for microelectronics have been used in producing microsystems components.1 However, we soon will realize microsystems packaging is much more complicated than that for microelectronics.
The purpose of microelectronics packaging is to provide mechanical support, electrical connection and protection to the integrated circuits (ICs) from all possible attacks from mechanical and environmental sources. It also involves removing excessive heat generated by the IC on the silicon die as well as mitigating the induced thermomechanical stresses due to mismatch of thermal expansion coefficients in the chip components.
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There generally are four levels in electronics systems packaging hierarchy. The first is the "chip and module" level, in which the IC on the silicon chip is packaged into modules. The second is the "card" level, at which the modules are packaged on the function cards. The next level involves the assembly of cards to the "boards." Level four involves assembling various boards to make the system.
We propose a three-level MEMS packaging strategy: (1) the die level, (2) the device level and (3) the systems level. Die-level packaging involves passivating and isolating the delicate and fragile sensing and actuating elements. The task also includes die and wire bonding in many cases. The device-level packaging involves power supply, signal transduction and interconnections. Systems-level packaging integrates MEMS devices with primary signal conditioning circuitry to customers' applications.
Die-level packaging
Major tasks involved in this level of packaging involve die passivation, die isolation and die bonding.
Die passivation: Since the die in microsystems often are required to be in direct contact with hostile working media, proper protection of these delicate die is critical to ensure the lasting function of the devices. There are several ways a die can be protected from toxic working media:
- Depositing a thin layer of organic substance such as Parylene over the exposed die surface. LPCVD can accomplish the deposition of layers ~2 or 3 µm thick. A negative effect of this form of passivation is that the added layer often makes the die too stiff for accurate sensing or actuating functions.
- Coating the die surface with soft substances such as silicone gel (Fig. 1). Hardening of the gel with time is a major problem of this method of die passivation.
- An overlay material (e.g., plastic) can be applied over the die, followed by providing the package with passages using laser ablation (Fig. 2).3,4 Figure 3 illustrates an effective method to protect a die by a surface micromachining technique.1,2 Thin layers (a few microns thick) of common sacrificial layer materials are first deposited over the die surface, followed by deposition of other materials such as polysilicon. The sacrificial materials are subsequently removed by etching, leaving a cavity between the die and the protective polysilicon for attachments, such as transducers and wire bonding.5 LPCVD is frequently used for this purpose.
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Die isolation can be achieved by mechanical design with optimum geometry and also with proper die attachments. For example, more fluxural in bending of the silicon die can be achieved by increasing the height of the die support to accommodate the difference in thermal expansion coefficients between the die and the base. Die attaches using soft materials such as silicone rubber also can improve die isolation.
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Die bonding: There are numerous ways in which die can be bonded to the constraint bases. Anodic bonding is a popular method to bond silicon to glass wafers. The process requires high dc voltage at 1 kV applied to the bi-layered material at a temperature of 450-900°C. Bonding silicon die to the glass bases using this process is both reliable and hermetic. Eutectic solder alloy (60 Sn-40 Pb) is used for die bonding. This process requires the bonding surfaces to be plated with noble metals in layers only fractions of a micron thick. Eutectic bonding results in reliable and hermetic seal, but has proven to be too rigid for die isolation in some applications. Another material for die bonding is epoxy resin. This method is popular for its ease in application, and it provides more flexibility for die isolation. However, epoxy resin has serious aging problems and is vulnerable to moisture and chemical attacks. The best die bonding material for die isolation is silicone rubber, which provides hermetic seals but has virtually no bonding strength in tension.
Device-level packaging
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Major tasks involved in this level include signal mapping and transduction, wire bonding, and component bonding. Signal mapping and transduction and transmission are essential parts of microdevices. Selection, fabrication, positioning and conditioning of transduction systems require careful design prior to device production. Figure 4 illustrates various transduction systems available for microsystems.
Proper electrical bridge circuits such as Wheatstone bridges are required for signal conversion and conditioning. Often, auxiliary circuitry is required to compensate for errors induced by mechanical hysteresis of the sensing materials or environmental effects such as temperature and moisture.
Signals produced by transducers in the die need to be connected to the interconnects. Conventional wire bonding techniques for microelectronics can be used for this purpose. These include popular techniques such as thermocompression, ultrasonic and thermosonic bonding.6 There is no set, standard technique for joining various components in a microdevice. Available techniques include 1) adhesion using epoxy resin and adhesives, 2) thermal fusion bonding of materials such as silicon at high temperatures, and 3) physical and chemical vapor deposition techniques commonly used in microelectronics. Soldering and welding are used in joining pieces for metal casings for robust packages.
Microsystems packaging engineering
Microsystems packaging involves four major engineering tasks: packaging design, fabrication, assembly and testing.
Packaging design: Design of microsystems requires integrating the theories and principles of electromechanical, mechanical materials, mechanical fabrication processes, and design for manufacturability and assembly.1
Essential packaging design considerations include design for minimizing costs in manufacturing, system assembly, electrical feed-through and die and wire bonds. Environmental effects and overcapacity are critical elements in the packaging design. Optimal selection of materials can have major impact on the overall cost of the package.
The complex geometry and loading and boundary conditions in packaging design analysis have made finite element method (FEM) the only viable tool for the purpose. More recently, commercial computer-aided packages such as IntelliSuite have been used in conjunction with the FEM. Tools for coupled electromechanical and electrochemical analyses, however, remain to be developed.
Fabrication of packages: Techniques for die passivation and isolation as presented have been developed and practiced by the industry. Bonding of various components in the package, however, remains a major problem.
Package assembly: The minute size of components to be assembled in the package presents an enormous challenge to engineers. A few techniques for self-assembly of parts in micro scales have been developed for mass production purposes. However, these techniques are in their infancy, and they are limited to the mating of simple geometry of the assembled microcomponents. Assembling components of micro and meso scale into integrated systems requires proper procedures and tools, which have yet to be developed.
Performance testing: Testing microsystems packages involves hermetic testing for leak of working media, electricity, optics and magnetic, depending on the function of the device. Packages also need to be tested for function reliability and robustness in field applications.
Major issues in microsystems packaging
As commercialization of MEMS and microsystems has gained momentum in recent years, product packaging has gained increasing attention from the industry and research community. There are numerous issues that require immediate attention by researchers and practicing engineers. Following are just a few of these.
Packaging design standards and methodology: Aside from certain types of pressure and inertia sensors used by the automotive industry, most MEMS and microsystems products are custom-built with batch productions. This has made standardizing design methodology virtually impossible at this time. However, it will be helpful if the industry and research/academic institutions can jointly develop sets of standards for designing basic components in common microdevices such as sensors, actuators and micro fluidics. One urgent issue in this development is the geometric tolerancing for the design and assembly of microdevices. Standardization of materials for fabricating and packaging these products will be of great value to the industry.
Package assembly: Bonding is a critical issue in microsystems assembly. Reliable techniques such as "micro-welding" free from residual effects need to be developed. Current bonding methods have serious drawbacks. Wire bonding is another area that requires further research. Alternative wire-bonding techniques will contribute significantly in miniaturizing packages.
Tools such as microassembly robots need to be developed for micro/meso packaging assemblies. These tools must be intelligent enough to handle the delicate and fragile components in micro scale in the package. A consideration is to develop adaptive intelligent micro end-effectors as an intermediate step toward full-blown microrobots.
Testing: Microdevices are designed to perform functions with sensitivity and precision. Two issues involved in this area: (1) test procedure for specific devices and applications, and (2) appropriate strategies and metrologies for the tests. Much research effort is needed to deal with these issues.
Interface of micro/meso components: It is inconceivable that a die in micro scale could be packaged into the same scale. Microdevices likely will be in meso scale in millimeters if not centimeters. The interface of components of significantly different sizes presents problems in fabrication and assembly. Viable design methodology for such interfaces in fabrication and assembly is an important development area.
Recommendations
Major barriers in the development of microsystems packaging technology can be attributed to the following:
- Lack of information and standards in materials, design methodologies, fabrication processes, assembly and testing.
- Short supply of engineering specialists with cross-disciplinary knowledge and experience in mechanical/electrical/ materials/process/software.
- Lack of opportunity to share and exchange experience and information in dedicated conferences and workshops.
- Lack of R&D support from public funding sources.
Immediate future needs in packaging will require much R&D effort in the following areas:
- Development of appropriate standards and design methodology for packaging.
- Availability of information on new and existing packaging materials.
- Improvements in bonding and lifting technologies.
- Development of new and effective assembly tools and methodologies.
- Improvement in the techniques for integrating micro (die level) and meso (device level) scale packaging.
E-mail: tairan@email.sjsu.edu
REFERENCES
- T.R. Hsu, "MEMS and Microsystems: Design & Manufacture," McGraw-Hill Co., Boston, 2002.
- M. Madou, "Fundamentals of Microfabrication," CRC Press, Orlando, Fla., 1997.
- L. Guerin, M.A. Schaer, R. Sachot, M. Dutoit, "New Multichip-on-Silicon Packaging Scheme for Microsystems," Sensors and Actuators, Vol. A52, 1996, p. 156-160.
- J.T. Butler, V.M. Bright, "An Embedded Overlay Concept for Microsystems Packaging," special section on microsystems packaging design, IEEE Trans. CPMT, Advanced Packaging, Vol. 23, No. 4, Nov. 2000, p. 617-622.
- L. Lin, "MEMS Post-Packaging by Localized Heating and Bonding," IEEE Trans. Adv. Packaging, Vol. 23, Nov. 2000, p.302-307.
- "Plastic-Encapsulated Microelectronics," ed. M.G. Pecht, L.T. Nguyen, E.B. Hakim, John Wiley & Sons Inc., 1995, Chapter 3.
The author gratefully acknowledges support for this development by part of a grant from the National Science Foundation (NSF Award No. DUE-9455395).
Based on "Packaging Design of Microsystems and Meso-scale Devices" by Tai-Ran Hsu, which appeared in IEEE Transactions on Advanced Packaging, vol. 23, no. 4, Nov. 2000, p. 596-601. ©2000 IEEE.
