Advanced Ion Implantation Brings New Changes

		At a Glance
	Advanced ion implantation techniques and the precise physical placement of dopants are being used to solve device scaling issues through the use of equivalent scaling methodology, and can also improve device performance with manufacturing cost reduction.

With the problems associated with continued conventional device scaling and the move to system-on-a-chip (SOC) with embedded memory and logic devices, the industry is facing a new paradigm shift. Conventional scaling has been reported to be less effective for sub-130 nm SOC technology, so the industry is moving to equivalent scaling.¹ Equivalent device scaling is achieved through 1) new materials such as silicon-on-insulator (SOI) wafers and higher-k gate materials; 2) new processes such as multiple gate oxides and shallow junction formation methods; and 3) new device structures such as notched poly, fully depleted/partially depleted (FD/PD) SOI, double gate and vertical transistors.

However, the realization of these approaches on improved device performance usually comes with higher manufacturing costs. Therefore, using a front-end-of-line (FEOL) device processing sequence, this paper will discuss how the use of advanced ion implantation techniques and the precise physical placement of implanted species can also solve equivalent scaling issues without the added higher manufacturing costs in the following areas:

• Wafer and isolation engineering for improved vertical and lateral device isolation.
• Gate material modification through ion implantation for multiple gate oxide thickness for embedded memory and logic technologies and to achieve higher-k gate dielectric to lower gate leakage.
• Channel and source/drain (S/D) engineering for shallow junction formation, gate overlap control and short channel effect (SCE) control.
• Process simplification and lithography mask count reduction.
• New advanced ion implanter designs to achieve these results.

Vertical, lateral isolation

The VIISta-10P2LAD is a single -wafer plasma implanter.

The first steps in device processing are wafer and isolation formation. Both lateral and vertical device isolation improvements can be realized through advanced implantation techniques. According to a recent paper,² there are three successful ways to manufacture thin SOI wafers. Of those, two techniques use ion implantation and the third uses silicon epitaxial growth.

Developed by Canon Inc. (Tokyo), ELTRAN (epitaxial layer transfer) grows a thin epitaxial layer on top of a porous silicon surface followed by wafer oxidation and bonding. This results in a very high-quality SOI wafer with an epitaxial layer for the top SOI surface that is free of COP (crystal originated particle) defects.

The method has demonstrated the superior quality of SOI devices formed in a top epitaxial SOI layer compared with using just a standard bulk Cz SOI surface top layer. The two implantation methods usually form the thin SOI top layer from a Cz bulk wafer. However, if COP defects and surface quality become an issue, both methods can use a silicon epitaxial wafer to achieve a top epitaxial SOI layer. This is now available on the SOI wafer market.

About 70-75% of thin SOI wafers are made with a hydrogen implantation step in high-current implanters for vertical isolation. This method uses hydrogen implantation (10¹⁶ atoms/cm²) to form a splitting buried layer in the SOI wafer bonding manufacturing method. SOITEC (Grenoble, France), Shin-Etsu Handotai Ltd. (SEH, Tokyo) and Silicon Genesis Corp. (SiGen, Campbell, Calif.) are three companies using hydrogen implantation for SOI wafer manufacturing.³

SIMOX (separation by implantation of oxygen) SOI wafers — manufactured by high-dose (10¹⁷-10¹⁸/cm²) oxygen implantation — make up about 20% of thin SOI wafers. It was first reported 20 years ago by researchers from NTT Corp. (Tokyo). In this technique, oxygen is implanted directly into the silicon wafer at elevated temperatures of 500-600°C and a buried oxide layer is formed by a high-temperature (1350°C), six-hour post-implant anneal/oxidation process.⁴ Ibis Technology Corp. (Danvers, Mass.), Nippon Steel Corp. (Tokyo) and Komatsu Electronic Materials Co. (Tokyo) are examples of SIMOX SOI wafer manufacturers. They use specially designed very high-dose oxygen implanters available from Ibis or Hitachi Ltd. (Tokyo).

After the starting wafer is selected (bulk Cz, epi or SOI wafer), shallow trench isolation (STI) lateral isolation structures are formed. Improved isolation characteristics can be achieved through optimized deep and shallow retrograde twin- and triple-well implantations.^{5, 6} But with continued scaling of the STI structure, the aspect ratio increases, making the trench gap fill process difficult and forcing companies to revisit selective epitaxial growth (SEG).^{7, 8} Also, high-energy ion implantation in the 2-3 MeV range is used to form deep triple wells for vertical well isolation, usually isolating the top p-well from the p-substrate inside a deep n-well.⁵ This triple well structure is typically used for DRAM, SRAM and flash memory, as well as embedded memory/logic circuits.

Although high-energy buried layer implant structures have been shown to improve latch-up, they can degrade other device parameters (n-well to substrate leakage and breakdown voltage) and must be carefully integrated to optimize well-to-buried-layer defect location, especially to achieve epi replacement.⁶ Therefore, to further increase device packing density and minimize lateral n+ to p+ isolation spacing while maintaining uniform across-wafer device electrical parametrics, non-shadowing implantation at 0° tilt angle is needed to replace both tilted quad and non-quad implants.^9-11

Non-shadowing equivalent scaling methods are becoming more critical as we scale to 100 and 70 nm, where n+ to p+ spacing of <300 and 200 nm are needed, respectively. Shadowing can be completely eliminated through 0° tilt implantation. However, a critical parameter for these implants is incident angle control and uniform beam parallelism across the wafer to ensure uniform channeled dopant profile across the wafer. This will result in very uniform across-wafer device electrical parametrics yielding high-dollar-value die per wafer.

Higher-k gate oxide material modification

After well and channel doping formation, the next step in the device process sequence is gate dielectric formation. SOC devices with embedded memory and logic devices require multiple (i.e., triple) gate oxide thicknesses, and one method reported to achieve this is through implanting various species of O, F or Ar to enhance or N to retard silicon oxidation rate. Goto et al reported on using F implantation to enhance silicon oxidation rate by as much as 2×, and Togo et al reported up to a 5× reduction in silicon oxidation rate with N implantation and up to a 1.8× enhancement with Ar.^{12, 13}

The most advanced devices today use oxynitride gate dielectrics; however, higher-k gate dielectrics will be needed at the 70-100 nm technology node.¹⁴ Because of problems with thermal and CVD higher-k material processing including nitrided oxides and metal oxides, a better manufacturing alternative is needed. These high-k amorphous deposited materials have been reported to recrystallize at temperatures above 800°C, degrading dielectric constant. They are also extremely sensitive to the silicon surface pre-clean treatment and surface cleaning residue prior to deposition.

Therefore, a promising alternative method is gate material modification through implanting controlled amounts of selected impurities into high-quality thin thermal oxides. Puchner et al reported on ultra-low-energy ion implantation of nitrogen into thin SiO₂ between 10 and 200 V to form oxynitride films.¹⁵ Krug et al also reported nitrogen implantation between 3 and 30 V into 1.0 nm oxides.¹⁶ Thin oxides 1.0 to 2.0 nm thick will require very low-energy implants in the 20 to 50 V range with nitrogen doses at the 10¹⁵/cm² level. This is beyond the capabilities of traditional beam-line ion implanters, so these processes are being developed on single-wafer plasma implant systems known as PLAD (plasma doping) or PIII (plasma immersion ion implantation).

A key advantage of oxynitride formation by plasma implantation over remote plasma nitridation (RPN) is the precise control of the nitrogen dose and depth into the oxide. These implantation methods also provide solutions to integration issues such as low-temperature processing and silicon surface pre-cleaning sensitivity because you start with a standard high-quality thermal SiO₂ film. And they provide the opportunity for future clustering with other single-wafer process chambers such as etch, CVD, PVD or RTP.

"The challenge here is not only to identify high-k dielectrics with improved leakage vs. capacitance characteristics, but also to identify dielectric formation techniques resulting in clean silicon-dielectric interfaces that maintain high inversion charge mobility and good transistor performance," said Mark Bohr of Intel.¹⁷ Also, low-k intermetal dielectric film formation with dielectric constants as low as 2.9 have been reported by implanting F into oxides.¹⁸

Channel, source/drain engineering

After gate stack formation comes device channel and S/D engineering. Retrograde channels for improved SCE is now standard practice using In and Sb for Vt implantation. However, because of residual defects and dopant solid solubility limits with these dopant species, companies are switching back to B, P and As. To maintain steep retrograde profiles, these implants can be done after gate stack formation, through gate implant (TGI) as reported by Ponomarev et al.¹⁹ HALO implants also modify the device channel and SDE (source/drain extension) profiles to improve SCE and reduce Vt roll-off.^{20, 21} Miyashita et al reported on improved SCE and Vt roll-off effects by using high-tilt HALO from 30° up to 60°.²² However, due to the gate stack height and gate stack to gate stack spacing, HALO implant angles are being reduced to <30° tilt. With optimized super-HALO implantation, retrograde channel Vt implants can be eliminated altogether as reported by Yeap et al of Motorola and Taur et al of IBM.^{23, 24}

The ITRS reports the need for ultra-shallow junction (USJ) for SDE with lower sheet resistance (Rs) as devices continue to scale. There has been some disagreement with the ITRS requirements for USJ at recent technical meetings of the April MRS 2000, September SSDM 2000, September IIT 2000 and December IEDM 2000 meetings. Gossmann et al reported that higher R values for SDE are acceptable to maintain the required device drive current.²⁵ Similarly, Kim et al reported that, as you continue to scale devices, the key contributor to total series resistance (R_series) will be S/D contact resistance (R_cont) and not SDE resistance (R_ext).^{26, 27} At the 100 nm node, R_ext and R_cont both equally contribute 40% each to R_series, while at 70 nm and below R_ext drops down to only 12% and R_cont increases to 60% of R_series.

However, if one still needs to form USJ with low resistance for SDE, there are two basic techniques: 1) ultra-low-energy (sub-keV) implantation by beam-line or plasma implantation followed by high-temperature, short-time annealing (1000-1100°C RTA/spike annealing); or 2) higher low-energy (1-2 keV) implantation followed by low-temperature (550-800°C) SPE (solid phase epitaxial regrowth/recrystalline) annealing. RTA/spike annealing will be used for 130 nm technology and may be extended down to 100 nm technology.²⁸

Laser annealing, on the other hand, has major process integration issues that will likely prevent its use in production. They include dopant solid solubility deactivation issues; control of localized wafer surface melting, especially on patterned device wafers with multiple material and layered structures such as STI; gate poly material melting issues; and temperature compatibility for use with high-k gate material.^{29, 30} Therefore, low-temperature SPE looks to be the best alternative solution for both ultra-shallow junction formation and high-k gate material process integration.

1. Beam-line (B₁₁ and BF₂) and PLAD (BF₃) as-implanted X_j junction depths.

With SPE annealing and no dopant diffusion/movement of the implanted dopant atoms, beam-line implantation can be extended down to 70 nm technology node and plasma implantation down to 35 nm node. Otherwise, beam-line can only be extended to 130 nm technology node and may need to be replaced at 100 nm technology node because of high-temperature dopant diffusion. This is illustrated in Tables 1 and 2 for high-temperature annealing and low-temperature annealing, respectively, where the implant energy required to achieve the desired ITRS X_j implant junction depth is shown. The data in Table 1 assumes a 2× diffusion in the as-implanted junction depth due to high-temperature annealing and TED (transient enhanced diffusion), which has been reported to vary between 15 and 50 nm, while Table 2 assumes no diffusion due to low-temperature annealing. The various as-implanted X_j values for beam-line B₁₁ or BF₂ and plasma BF₃ implants were taken from Lenoble et al (Fig. 1).³¹ With plasma implantation (PLAD) and either high-temperature or low-temperature annealing, we can achieve 35 nm node shallow junctions. If, however, the industry switches to low-temperature SPE sooner for various process integration reasons — including high-k gate material temperature compatibility — then beam-line B₁₁ implant energies can be increased to 1.5 keV for 130 nm node, and 250 eV will not be needed until 70 nm node.

Table 1. Junction Depth from High-Temperature Diffusion/Annealing
(Assume 2x as-implanted Xj)
	130 nm	100 nm	70 nm	50 nm	35 nm
Xj	25-45 nm	20-35 nm	16-26 nm	12-20 nm	8-14 nm
Rs	250-700	200-600	150-500	120-450	100-400
B11	0-250 eV	——	——	——	——
Actual	500 eV-1 keV	200-600 eV
+Ge-PAI	<2 keV	500 eV
BF2	0.25-2.5 keV	0-750 eV	0-200 eV	——	——
Actual	1-3 keV	——
PLAD	0.5-1.5 kV	400-800 V	100-500 V	75-400 V	50-80 V
Actual	——	600 V
+PAI	1-2 kV	0.6-1.2 kV	500-900 V	400-800 V	200-400 V
130 nm and 100nm examples actually being used, Borland January 2001

 

Table 2. As-Implanted Junction for Low-Temperature SPE Annealing
	130 nm	100 nm	70 nm	50 nm	35 nm
Xj	25-45 nm	20-35 nm	16-26 nm	12-20 nm	8-14 nm
Rs	250-700	200-600	150-500	120-450	100-400
B11	0.25-1.5 keV	0-1 keV	0-250 eV	——	——
BF2	2.5-7 keV	2-5 keV	0.75-2.5 keV	0.25-2 keV	0-250 eV
PLAD	1.5-3 kV	1-2.5 kV	0.75-1.5 kV	0.5-1 kV	100-500 V
+PAI	2-5 kV	2-4 kV	1-2 kV	1-2 kV	0.5-1 kV

2. State-of-the-art Rs-vs.-X_j results using low-temperature SPE at <600°C.^35-38

In a survey recently conducted by the author and identified in Table 1 as "actual" implementation clearly shows, B₁₁ will be used exclusively because of the lack of interest in using BF₂ implants below 1 keV for the 100 nm node. Bourdelle et al reported on the negative effects on BF₂ vs. B₁₁ implantation on thin gate oxides below 2.2 nm.³² Others have also observed and reported similar F effects from BF₂ implantation compared with B₁₁ on thicker gate oxide of ~5.0 nm as reported by Ha et al.³³ The main concern with implementing low-temperature SPE in manufacturing is junction leakage and, therefore, location of residual implant damage. However, there have been several reports on solving the leakage issues with low-temperature processing.^{34, 35} To date, the state-of-the-art Rs-vs.-X_j results using low-temperature SPE at <600°C is shown in Figure 2 corresponding to ~2 × 10²⁰/cm³, while the limit from RTA anneals as first reported by Shichiguchi et al is ~8 × 10¹⁹/cm³.^{36, 38}

3. Parallel beam vs. beam blow-up (divergence) at 0° tilt angle.

To maximize implanter productivity and avoid photoresist shadowing and quad implantation, both shallow SDE and deeper S/D implants are done at 0° tilt and, as described earlier in the isolation section of this paper, incident angle variation across the wafer can result in both de-chaneling and gate stack shadowing variation across the wafer, affecting dopant profile. For example, a 1° tilt angle variation has been reported to cause as much as a 5% Vt shift. In addition to batch implanter cone angle effects on across-wafer tilt and twist implant angle variation, during low-energy implantation the beam size/spot blows up and diverges as the implanter is operated in low-energy mode, and the beam angle spread can vary from as little as 2° to as much as 15° (Fig. 3 illustrates a 2-5° spread). This can result in worst-case localized implant tilt angle variation under the gate stack structure of ±15.0° in the center of the wafer. When you add in the cone angle tilt effects on a batch implanter (±1.5°), you can end up with +13.5° to -16.5° for devices on the right side of the wafer to +16.5° to -13.5° for devices on the left side, resulting in assymetrical SDE structures around the gate stack structures across the wafer, affecting uniformity of device parametric performance. Also, energy contamination can occur during implant decel mode of operation, as reported by Murooka et al for a 500 eV implant in drift vs. decel mode.³⁹ It was shown that 0.3% energy contamination can result in a 20% as-implanted junction depth change. Also, Lenoble et al showed channeling vs. non-channeling profiles for implants into crystalline or PAI (pre-amorphous implant) wafers.³¹ The channeled dopant profile was 36% deeper in the crystalline sample for a 1 keV boron implant compared with a PAI wafer.

Using the 100 nm ITRS node as a reference point, Osburn simulated the effects of SDE implant dose, energy and tilt angle variation on both NMOS and PMOS device parametrics.⁴⁵ Tables 3 and 4 summarize his results for implant dose, energy and tilt angle sensitivity for PMOS and NMOS devices, respectively, for various electrical parametric values (D Vt, D I_off/I_off and D I_dsat/I_dsat). The results clearly showed that implant tilt angle control had the greatest impact on device parametric shift. Al-Bayati et al reported that a 1% energy contamination results in a 1% Vt shift, 2% L_eff and 3% I_dsat.⁴¹

Table 3. Implant Dose, Energy and Tilt Angle Effects on PMOS Device Parametrics (Ref. 40)
	D I off /I off	D I d sat /I d sat	D Vt
Dose	1.7%/%	0.14%/%	0.3 mV/%
Energy	-2.4%/%	-0.29%/%	0.5 mV/%
Angle	-9.4%/°	-0.64%/°	1.9 mV/°
— Dose and energy variations have minor impact. — Tilt angle is the most important parameter to control.

Table 4. Implant Dose, Energy and Tilt Angle Effects on NMOS Device Parametrics (Ref. 40)
	D loff /I off	D ld sat /I d sat	D Vt
Dose	-2.6%/%	0.078%/%	-0.85 mV/%
Energy	-0.059%/%	0.007%/%	0.071 mV/%
Angle	16.1%/°	1.68%/°	-2.15 mV/°
— Dose and energy variations have minor impact. — Tilt angle is the most important parameter to control.

Process simplification

The need for retrograde channels was described above. However, a new trend is to do this pre-gate Vt implant post-gate for process simplification and mask reduction.¹⁹ This has been implemented into manufacturing by several companies around the world, starting at 0.22 and 0.18 µm CMOS technology for logic and memory devices; more companies will implement this at 0.13 µm.⁴²

4. When combined with high-tilt SDE implantation, this PoGI (post-gate implant) process simplification structure can eliminate up to four masking levels in twin well CMOS FEOL processing.

When combined with high-tilt SDE implantation, this PoGI (post-gate implant) process simplification structure (Fig. 4) can reduce up to four masking levels in twin well CMOS FEOL processing.⁴³ The first key factor for success of the PoGI process is high-tilt, high-current SDE implant through the sidewall spacer, and the second is either Vt implant through the gate stack structure or use of super HALO in place of Vt implants as reported by Yeap et al and Taur et al.^{23, 24}

In the literature there are several process simplification reports using high-tilt implantation for LDD, MDD, HDD and SDE formation.^44-47 High-tilt implantation of LDD structures through sidewall spacers were first used for manufacturing back at 0.35 µm technology by several companies using medium-current high-tilt implanters. With the availability today of high-current high-tilt implanters, this process can now be continued for SDE formation. Through gate implantation with disposable spacer processing for mask count reduction has also been reported.^{48, 49} Therefore, high-tilt SDE implantation allows precise positioning of the SDE structure for gate overlap control with optimum device performance, and this technique can also be used with a notch poly gate stack structure.^50-52

Summary

This paper discussed how the use of advanced ion implantation techniques with precise physical placement of these species is solving equivalent device scaling issues in the areas of 1) wafer and isolation engineering for improved device vertical and lateral isolation; 2) higher-k gate material modification to lower gate leakage; 3) channel and S/D engineering for shallow junction formation and gate overlap control; 4) PoGI process simplification and lithography mask count reduction; and 5) new advanced ion implanter designs driven by 300 mm wafers and new implant cluster tool possibilities.

These techniques can also improve device performance and reduce manufacturing costs. Using single-wafer high-energy and high-current designs with tight control over incident angle with uniform beam parallelism can result in extremely uniform across wafer device electrical parametric control, which is becoming more critical for continued device scaling. Using plasma doping techniques with SPE low-temperature annealing, we have demonstrated 50 nm technology node shallow junction requirements.

Also, plasma implantation of non-dopant species for surface material modification applications clustered to etch, CVD, PVD or RTP chambers will dramatically change the way implanters and cluster tools are designed in the future.

John O. Borland is director of advanced business development at Varian Semiconductor Equipment Associates Inc.
E-mail: john.borland@vsea.com

---

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Acknowledgements

The author is grateful for technical discussions with numerous technologists from various companies around the world, including J.W. Park of Samsung; S. Saito of NEC; M. Kase of Fujitsu; T. Kuroi of Mitsubishi; C. Diaz and H. Chang of TSMC; D. Lenoble of CNET/ST; D. Jacobson, H. Gossmann and C. Rafferty of Agere; R. Mann, D. Sadana and Y. Taur of IBM; A. Wittkower of SOITEC; C. Osburn of North Carolina State University; N. Cheung of the University of California (Berkeley); and S. Felch, R. Liebert, S. Walther and A. Bertuch of VSEA.

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