Thermal Processing Copes With Limits, Materials
Alexander E. Braun, Senior Editor -- Semiconductor International, 4/1/2001
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At a Glance | | |
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"Predictions for gate oxide's end have shifted from about 80 Å in the early 1980s, to the low 20s," said Robert Soave, marketing manager for the diffusion systems division of TEL America (Austin, Texas). "Now we're growing <20 Å gate dielectric for 0.13 µm applications, and producing viable SiO2 gate dielectrics well below 15 Å in specially configured batch furnaces."
Paul Meissner, vice president of thermal systems and modules at Applied Materials (Santa Clara, Calif.), is seeing a shift from batch to single-wafer processing. "At 200 mm, most chipmakers use RTP for standard processes: implant, anneals, ultrashallow junction, cobalt, etc.," he said. "The introduction and acceptance of our LPCVD chambers for nitride and high-temperature oxide (HTO) and polysilicon processes provide the option to use single-wafer tools for the entire FEOL operation. Many manufacturers moving to 300 mm see technical and economic benefits in using single-wafer processing."
Nitin Shah, product line manager, RTP, for Axcelis Technologies (Beverly, Mass.), sees four RTP drivers: device shrink; 300 mm wafers; new materials' process challenges; and thermal budget requirements, pushing applications to lower temperatures and medium-time processing.
RTP technology is changing, explained Andreas Toennis, RTP general manager for Mattson Technology (Fremont, Calif.). "There's the traditional lamp-based single-wafer platform, but susceptor-based RTP is moving into production," he said.
Consolidating processes
Applied now offers a single-wafer product suite that supports the capability to do all the thermal oxidation and diffusion steps in the same chamber, while another performs all the LPCVD nitride, HTO and polysilicon deposition steps.
With RTP's closed-loop temperature control and emissivity independence, precise control of ultrashallow junction depth and lower thermal budgets are achieved.
"Take shallow junction — we've met the challenge because we have sufficient ramp-up and ramp-down rates in our RTP," said Meissner. "Doing a uniform low-temperature nitride — impossible for a furnace with today's current chemistries — is key for a production-quality spacer."
TEL reported that it is production-qualifying a 600°C batch CVD silicon nitride process that uses a proprietary low-temperature chemistry. The process would be used for sidewall spacer applications at 0.13 µm.
Solutions exist for every step of the 0.13 and 0.10 µm nodes. "As manufacturers shift to 300 mm, they want to know if it's economically sound to go from batch to single-wafer," said Meissner, adding that single-wafer equipment saves on cost of ownership and also reduces time to market and cycle time — a fab can get started two months ahead of schedule.
Strategically, everything can be qualified at 0.13 µm on 200 mm. Then, when scaling to 300 mm, all production is done on single-wafer, obtaining technology and cycle-time benefits. Primary hurdles center around ultrashallow junction and gate scaling; others, like thermal-budget-driven LPCVD steps, are enablers, not roadblocks.
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"There's a drive to lower-temperature LPCVD," said Meissner. "Say you have a spacer process running at 700°C in a furnace, vs. 700°C in a single-wafer system. You're already an order of magnitude lower thermal exposure with a single-wafer process — minutes vs. hours" (Fig. 2).
With the shift to shallower junctions and new materials, there is pressure to reduce deposition temperatures to below 680°C. The challenge will be to show that this single-wafer advantage will extend to lower temperatures with comparable uniformity, particle, repeatability and CoO performances.
"Everyone's considering alternative chemistries," said Meissner, "due to the fact LPCVD nitride chemistries of monosilane and ammonia will have issues as deposition temperatures drop toward 600°C — we're exploring alternative chemistries."
Much remains to be done with CVD before resorting to something like ALD, and Meissner is skeptical about whether ALD's throughput will ever be practical for thick films.
Everyone is focusing on the gate-shrinking dielectric thickness while maintaining good leakage current performance and channel mobility. Meissner said that he believes it is likely that SiO2 is extendable to 0.10 µm and below.
"You use nitrogen (because of the bonding at the interface) to improve leakage performance and effective oxide thickness by changing the dielectric constant," he said. "Thus, you have a physically thicker film but one that behaves electrically, as if it were physically thinner — simple engineering that can be done with a single-wafer decoupled plasma nitridation chamber."
When oxidation runs out, R&D will be necessary. "Can you go to a straight high-k film deposited right on the semiconductor, or is extensive interface engineering required?" wondered Meissner. "Speaking from experience with tantalum oxide, when we finished the chamber development it took a long time to help users qualify it for production, due to the interface engineering required once you put the film down. It'll be the same for high-k."
"When a furnace's process cost per wafer (CPW) comes under fire because of long cycle times, single-wafer offers better alternatives," said ASM's Werkhoven. "This is because of single-wafer's logistic benefits: Only one cassette is needed to start on a machine waiting for the next step."
Werkhoven added that waiting time is costly and becomes significant when added to a platform's CPW. With increasing varieties of processes and products in foundries, manufacturers are looking to the more flexible single-wafer approach, particularly when one cassette needs a certain process and the next needs another. That is why ASM now offers both alternatives, addressing specific markets and applications.
Fig. 3). While faster handler and heater design requires simple engineering, the biggest hurdle for new materials — exotic dielectrics, both low- and high-k — is integration, usually attained by empirical experiments.
For example, although the deposition process is straightforward, it took 10 years to integrate epitaxy of SiGe into a working hot device. Requirements now go beyond wafer uniformity, including electrical specs that are measurable only on finished devices.
Lamp vs. hot wall
Although single-wafer processing is the trend, Axcelis' Shah sees a bottleneck. "It relates to shorter times and higher temperatures, and maintaining uniformity across the wafer," he said. "RTP's major hurdles are temperature measurement and control and preserving across-wafer uniformity for emerging short-time, high-temperature processing, including ultrashallow junction annealing and STI corner rounding. Additionally, these tools need to be robust enough to produce repeatable results for the different wafers and backsides that will be processed."
Axcelis believes the hot-wall RTP approach is superior to lamp-based systems, especially for 300 mm. "A lamp-based system requires the control of multiple banks of lamps," said Shah. "It's also difficult to scale up because the system is far from thermal equilibrium, making it fundamentally harder to obtain across-the-wafer uniformity. This requires complex temperature measurement and control to achieve results for 0.10 µm. Being closer to thermal equilibrium, a hot-wall system delivers inherent thermal uniformity, simplifying control."
Mark Finocchario, president of Kokusai Semiconductor Equipment (San Jose), sees the thermal processing area splintering into three pieces: large batch, small batch and single-wafer processing.
"Drivers are cost of ownership and process requirements such as ambient control features (O2 and H2O control) and thermal budgets," he said. "In addition, process cycle time varies significantly between large-batch and single-wafer tools. Shorter cycle times are more compatible with the manufacturing process flows used in fabs that run a large number of different products."
Larger wafers pose film uniformity challenges at 0.13 µm and below. "Temperature uniformity is key to film uniformity control and composition," said Finocchario. "Improving particle control in a batch hot wall reactor extends its lifetime. Although <15 Å SiO2 gates have been demonstrated in batch, it's not clear whether they can be manufactured consistently."
Dielectrics and thermal budgets
IBM Microelectronics (Essex Junction, Vt.), has had copper in production since 1998. In terms of thermal budgets, IBM has for years used a copper-compatible BEOL processing regime with a maximum temperature of ~400°C, said Jim Ryan, manager of interconnect technology.
"This differs from some others who used higher temperatures, around 425°C or 450°C. We've gone with SiLK spin-on dielectric, which is compatible with 400°C processing," he explained. "Long term, thermal budgets will decrease even as the number of operations in the BEOL-interconnect area increase. Chips proposed for 0.13 µm require eight or more levels of wiring if you include local interconnects and straps on the gate."
The prospect is for several operations to be carried out at that temperature, with changes to transition into lower and lower dielectric constants. "The first approach will be to try to use older processes," Ryan added. "Those tools are already in the fab and, as developments progress, some production tooling can be shared. You only attempt another temperature or process when what you're using no longer works."
As a first approximation, 400°C processing will be tried. "The problem is that some dielectrics must be cured at a higher temperature," said Ryan. "However, I don't know whether that makes for the best integrated system because with a polymer dielectric, for instance, you have an adhesion promoter, then a polymer dielectric, and then some inorganic dielectric on top of that. Parts of that laminate structure are compatible with high-temperature processing; others aren't, so you must select a temperature that enables you to build the whole structure."
Fig. 4), said Mattson's Toennis. "There's more use for anneals, especially shallow junctions, for oxidation-type processes — particularly newer ones with steam oxidation — for STI liner formation. There's a move toward selective oxidation using steam in a hydrogen-rich ambient."
Certain thermal processes have limitations that may create problems with new materials. There is some doubt whether in one or two nodes conventional doping and annealing technologies — ion implantation and RTP — can meet ultrashallow junction formation requirements, especially source and drain. "We'll probably meet 0.10 µm node requirements," said Toennis. "Beyond that, everyone's scratching his head."
Investing in annealing
"When copper annealing started, most worked in the 350°C to 400°C range — or higher," said Tom Ritzdorf, director of ECD technology at Semitool (Kalispell, Mont). "Then self-annealing recrystallization was discovered, pointing the way to lower temperatures."
Since then, most have moved to a 300°C maximum range. "This is compatible with low-k dielectrics, which must be processed under 380°C or 400°C," said Ritzdorf. "Equipment will follow suit. Presently, thermal equipment that is already in the fab is reused — single-wafer hot-plate type annealing processes, RTP processes optimized for different areas of the temperature regime, and many still use batch furnaces. Not much is invested in annealing."
The trend is toward integrated tool sets combining ECD and annealing in one platform. Ritzdorf considers this logical. "You derive several benefits. The timing of when you start the self-annealing process or recrystallization is immediate, providing consistent results."
In terms of grain size and electromigration resistance, annealing is characterized as a function of time at temperature. A major problem is incomplete knowledge about the basic processes.
"Many papers have been published since recrystallization and self-annealing were reported," said Ritzdorf, "but there's little fundamental understanding of what happens in terms of mobility of contaminants — dopants — in the copper, or of the mobility of crystalline defects, which can agglomerate and lead to macroscopic defects. We've discovered empirically we can have a huge impact on CMP rates, that large grain sizes can be induced with thermal processing and that electrodeposited copper undergoes some grain growth on its own without a thermal push."
While few are prepared to invest the effort to reduce annealing to a couple of elegant equations, the process must be sufficiently understood to solve future integration issues, such as when several thermal processes are incorporated with barrier/seed processes.
"Changing how things are done requires a solid knowledge about why we get the defects that we do when we incorporate processes," Ritzdorf said. "We're focused on interfaces and — particularly with copper — most troubles are integration problems."
Interfaces are determined by at least two processes — more, if deposition is followed by a patterning and a clean process and then another deposition process to form the next interface.
New fabs and single-wafer
Alan Emami, vice president of marketing for the thermal division of Silicon Valley Group (SVG, San Jose), sees the transition to 300 mm fabs speeding up.
"Cost of ownership-sensitive fabs are interested in continuing processing with vertical furnaces," he said. "They're joining us to extend the gates to 20 Å and below, using vertical furnaces."
SVG believes some fabs will still work with vertical furnaces while others, focused on more advanced film for 0.13 and <0.10 µm technology, will use single-wafer platforms.
SVG is working on a product called Xcelerate, which it says incorporates the vertical furnace's advantages into a single-wafer platform. It uses hot walls and enables the transfer of some of those traditional batch processes, such as DCS-based nitride, which cannot be done in lamp-based systems because of film and deposition chemistry characteristics.
Bob Herring, SVG's director of process technology, indicated that SVG is working on new requirements and processes for the 0.13 and 0.10 µm nodes. "Particularly developments that will come in at 0.13 µm, such as the shift from a gate electrode being a polysilicon strapped with silicide, to a polysilicon strapped by refractory metal."
What has been done is pattern and then oxidize the poly's sidewall. With silicide this is a straightforward process, but the refractory metal requires a hydrogen-rich selective oxidation process. In the gates stack area, most expect gate oxide with a post-oxide anneal with nitric oxide to continue for at least another generation.
"We've worked down to 1.5 nm with good electrical results in of tunneling leakage and breakdown voltage," said Herring.
The target is uniformity. As SVG's Emami puts it, "In a furnace in a large batch, with DCS-based thin nitride for capacitor dielectrics, it's possible to achieve about 3%, 3d, within-wafer uniformities. For 0.13 µm and under, manufacturers want a process that'll get below that. By taking that dichlor process to a single-wafer mode, we're taking uniformity down to a half to two-thirds of what is achievable with batch systems."
As the shift from batch to single-wafer processes progresses, ramp rate timescales shorten. Although assisted by gas flow digital controllers and other developments, integration into the fab is not straightforward.
"There was a move to replace thermal processing with APCVD-type processes," said Emami. "The transition from locos oxide isolation to shallow trench isolation is an example: We can fill gaps high-end tools such as HDP cannot do as well. The transition to plasma hits a wall with high aspect ratios — due to processing physics and chemistries. Older technologies, such as APCVD, can still do amazing things."
As devices scale down and shallow-trench aspect ratios increase from 4:1 to 6:1, HDP is limited by sidewall sputtering that creates a nodule on the trench top, sealing it and trapping a void. According to SVG, this does not happen with APCVD, making it possible, at <0.10 µm, to fill trenches even at 8:1 and 10:1 ratios.
No fundamental issues
TEL's Soave sees only engineering barriers to worry about. "Whether it's circuit design or material modification, we're finding ways to extend oxide. However, every film's fundamental limit is one monolayer, and there aren't suitable alternatives in sight. When you're growing something that thin, you need the right material properties, but beyond that it's all process control. We've provided extremely good Cpk values for <15 Å oxides."
Gate electrode changes will be necessary to minimize the poly depletion effect — a quantum mechanics result that transforms the oxide and the poly interface into an extra insulator, limiting gate oxide scaling effects. Until the magic material is found or developed, existing technologies must buy time.
"You're trying to replace 40 years' experience with nature's finest insulator in five years. Finding an acceptable, manufacturable, cost-effective SiO2 replacement won't be simple," warned Soave.
There is speculation about changing fundamental device architectures by doing the gate in an unusual way, such as replacement or damascene gate. "I'd also look at different channel engineering, with perhaps SiGe, to improve drive current using quantum effects," Soave said. He added that he believes traditional scaling will continue beyond 0.10 µm, with "interesting" designs and material treatments that allow the extension of SiO2-based gate dielectrics, with batch furnaces playing a major front-end role.
"If you consider the chemical regimes you must apply for reasonable throughput using single-wafer, they're high pressure and temperature — basically the kinetic equivalent of popping corn," said an industry observer. "We gravitated toward certain chemistries because they worked well for those materials. If you consider a hot-wall batch furnace's heat transfer mechanism, it can supply exceedingly good temperature control. To change everything in a short period to non-isothermal heat transfer and alternate chemical regimes is a daunting task."
As manufacturing approaches fundamental limits, a sense of alarm is developing. A design engineer put it best: "We've always been able to fool Mother Nature, and she's getting upset. Back in 1979, when etching vias we thought dimensions were tight with a 6 µm-wide hole. Gloom and doom was predicted under 1.0 µm, but each time we managed to be highly innovative."
How innovative the industry can get with quantum mechanical effects remains to be seen.
Applied Materials
