Optimize Wafer Thickness for 450 mm
Wafer thickness significantly affects costs and yield in wafer and device manufacturing. To avoid the problems experienced at 300 mm, the optimum thickness for 450 mm must be targeted.
Tadashi Kanda, Toshiyuki Fujiwara and Kazushige Takaishi, SUMCO Corp., Tokyo -- Semiconductor International, 12/1/2008
The process of making production-worthy 450 mm wafers includes the risk of dislocation loss, crystal defect control during a lengthy growth process, and development of appropriate crystal pullers and quartz crucibles, and degradation of wafer flatness. We have studied optimal wafer thickness for 450 mm wafers based on gravitational bending (sag), different support methods, vibrational effects and other practical considerations.
Crystal growing extension
The typical silicon wafer manufacturing process chiefly consists of production of a dislocation-free single crystal through the Czochralski method (Cz) using ultrapure polysilicon material, followed by a shaping process that slices the resulting ingot into individual wafers that are then polished. Going to the larger 450 mm diameter is not merely a size change, but is expected to cause key technical wafer processing challenges that will not be overcome by simply extending 300 mm technology.
The Cz process to produce a silicon single crystal starts from a neck process with a reduced growing diameter of a few millimeters to ensure dislocation-free integrity. It is then followed by shoulder (top) and body growth, and finally by the termination at the ingot’s tail section. The silicon crystal ingot is grown with a slightly larger diameter than that of the wafer to account for diameter fluctuation resulting from the slight variation of process conditions during growth. The Cz process typically results in some amount of silicon melt residual in the quartz crucible at the conclusion of the crystal growing process. Therefore, material loss in the Cz process results from four sections: the shoulder, the tail, the diameter overgrowth and the residual silicon melt.
We estimate material loss rates for 450 mm silicon ingots will be comparable to those for 300 mm (Fig. 1). A 450 mm ingot is comparable to the diameter of a regulation basketball hoop, and its length is about that of the hoop’s height from the floor. At these dimensions, the ingot weighs ~1 metric ton. This means that its small-diameter neck will not support it, requiring innovative ways in which to perform the growth process.
| 1. Scaling to 450 mm using the CZ method leads to a significantly larger, heavier crystal that requires much longer to grow and cool. |
The industry will need sufficiently massive quartz crucibles to hold and grow such heavy crystals. For 300 mm, 32 in. diameter quartz crucibles are standard. However, 450 mm silicon crystal growth will require crucibles 40-44 in. in diameter. In addition to this significant size increase, crucible quality would have to be improved to withstand extremely long crystal growing times. Producing such a large high-quality crucible manufacturing process will require significant efforts and resources before serious Cz process development can be considered.
Although today’s advanced crystal growing processes are relatively mature, disturbances such as earthquakes can introduce dislocations during Cz production. When such an event occurs, the partially grown crystal must be remelted and the process restarted. This is costly and time-consuming. One study indicates that 450 mm crystal growing process times would be approximately twice as long as those for 300 mm. This additional growth time increases the chance of loss due to dislocation caused by disturbances during the process.
There is also concern that 450 mm might have an impact on intrinsic defects introduced during the growing process. The crystal growing process’s thermal history determines the distribution, size and density of such crystal defects, which include crystal-originated particles (COPs), oxygen-induced stacking faults (OSFs), oxygen precipitates and others. In the case of 450 mm, there will also be a slower crystal cooling rate, extending the critical time when crystal defects form (2-4× that for 300 mm). This can increase defect sizes and/or densities, as well as introduce unknown crystal defects.
Therefore, hurdles for 450 mm include the development of appropriate crystal pullers and quartz crucibles, dislocation loss risk, and crystal defect control, to name a few. Compared with the diameter transition from 200 mm to 300 mm, 450 mm presents much more difficult problems to solve.
Wafer shaping challenges
The 300 mm format was initially adopted for the 130 nm node, and double-sided polishing (DSP) technology was simultaneously introduced as a standard process. DSP, which used a uniform polishing motion trajectory and radial polishing pressure, overcame the flatness limitations of single-sided polishing (SSP) technology. Consequently, in just six years, DSP technology and further process improvements met biannual flatness improvement requirements for device process generations down to 45 nm (Fig. 2). This advancement was the result of hard-earned process innovation rather than a windfall from the migration to 300 mm.
Although 450 mm is projected for adoption for aggressive device generation, a simple scale-up of existing 300 mm process technology would result in flatness degradation. There is currently no established process technology that meets this advanced device generation requirement; no innovative technology comparable to the introduction of DSP exists to ensure the projected flatness requirement will be met within this timeframe. It is uncertain how many years will be needed to meet this 450 mm requirement.
Wafer thickness concerns
Although introduced for the 130 nm device generation, 300 mm was expected to meet needs well beyond the 45 nm generation. With the progression beyond 45 nm, flatness and nanotopography requirements are expected to be even finer, requiring continuous improvements in wafer processing. Additionally, device processing is experiencing problems such as degraded flatness due to chucking (the chuck shape is in part translated to the wafer’s active region, influencing nanotopography and later impacting the lithography process). Another issue is thermal distortion and the resulting slip generation in the wafer during quick thermal annealing such as flash (millisecond) anneal.
Wafer thickness was standardized at 725 µm for 200 mm and 775 µm for 300 mm. The standardization of 300 mm thickness was arrived at somewhat arbitrarily. There were insufficient scientific and industrial considerations made for practical manufacturing to address the problems mentioned. Notably, wafer breakage during wafer shaping and device processes initially occurred at a higher frequency for 300 mm than for 200 mm or smaller wafers. This is also true for slip formation during the device process. Similar problems with the progress toward today’s advanced generations (65-45 nm) led us to question whether 300 mm wafer thickness is too thin to tolerate extendibility, and we researched the appropriate thickness for 450 mm wafers using single-crystal silicon wafers in parallel, and applying a numerical simulation analysis.
Gravitational bending
Many characteristics are affected by wafer thickness. Gravitational effects are an important consideration in horizontal handling during wafer shaping and device manufacturing. We define gravitational bending as the distance between a wafer’s highest and lowest points. Figure 3 shows the effect of gravitational bending on various thicknesses of peripherally supported wafers; wafers supported by front-opening shipping box (FOSB) and fork supports. This deflection was measured using a laser displacement gauge with X-Y scanning capability with an accuracy of ±10 µm. Depending on wafer thickness, the extent of bending varies widely. From our results, it appears that a thickness of ~1800 µm is necessary, using the peripheral support structure for 450 mm to maintain a bending coefficient comparable to that of its 775 µm thick 300 mm counterpart. We also investigated wafers with thicknesses of 825-1800 µm with different support methods. When a FOSB was used, minimal gravitational bending of a 450 mm wafer was observed with thickness of 1470 µm.
Using fork support, the relationship between wafer thickness and gravitational bending depends on the fork spacing. With spacings of 400 and 300 mm, minimum gravitational bending occurred with wafer thickness values of 1330 and 1060 µm, respectively. We did not see a minimum gravitational bending for the range of prepared wafer thickness levels with 200 mm fork spacing. Based on these results, minimum gravitational bending occurs for wafer thickness values of <825 µm for this spacing.
The combined value of wafer thickness and gravitational bending is strongly influenced by the support methodology. The combined value of wafer thickness and gravitational bending influences the wafer pitch within FOSBs. If pitch is increased to account for this phenomenon, it results in a larger and heavier FOSB. This relationship will have to be considered when determining wafer thickness.
Thin-film deposition warp
Epitaxial wafers will be used for 450 mm. These are characterized by a vapor phase layer several microns thick grown on a silicon substrate. Generally, there is some dopant impurity (boron or phosphorus) concentration difference between the epitaxial layer and the substrate. This concentration difference induces wafer warp due to lattice mismatch between the epitaxial layer and substrate. Figure 4 shows a numerically simulated example of such generated wafer warp. Assuming a 5 mΩ-cm substrate resistivity for a typical p/p++ epitaxial wafer, a thickness value of >1020 µm is needed for a 2 µm epitaxial layer thickness to meet the projected 30 µm maximum warp requirement of a 45 nm node device. A value of >1430 µm would be needed for a 4 µm epitaxial layer thickness to meet this 30 µm or lower wafer warp value.
Other thin-film device processes not associated with 450 mm production face similar warp issues as epitaxial wafers. These largely originate from thermal expansion coefficients and film stress differences induced by various thin-film depositions. Figure 5 shows a numerically simulated wafer warp value assuming a 100 nm silicon nitride layer on a silicon substrate. A thickness value of 1180 µm is needed to suppress warp on a 450 mm wafer to the level of a 775 µm thick 300 mm wafer.
| 5. Simulated wafer deflection (right) as a result of nitride film deposition (thickness = 100 nm, film stress = 1 GPa). |
In epi and thin-film deposition processes, appropriate thickness value for 450 mm could be set as a function of film thickness levels.
Vibration during transportation
We analyzed vibration factors for silicon wafers, simulating truck transportation. The dependence on wafer thickness of the natural frequency considering two FOSB wafer support approaches was examined. Figure 6 shows this relationship for the support layouts. A 450 mm thickness with a comparable natural frequency to a 775 µm thick 300 mm wafer is ~1800 µm, including gravitational bending.
Figure 7 shows a published example of the vibration frequency of cargo during truck transportation1 with a peak around 33 Hz. The corresponding wafer thickness necessary at a 33 Hz vibration is shown in Figure 6. Based on our results, this translates to wafer thickness values somewhere between 1050 and 1400 µm, depending on the support.
Figure 8 shows maximum displacement simulated examples for a 925 µm thick wafer experiencing a 1 G sine wave vibration; there is significant displacement around the resonance frequency. Once a resonance oscillation establishes itself during truck transportation, there could be wafer contact with supporting points and/or neighboring wafers; much remains to be done to solve anticipated 450 mm wafer shipping problems.
Shaping problems
Higher wafer thickness values are better for yields in slicing and lapping processes while marginally thick ones are a concern for in-process transportation, as well as for epitaxial and thermal processes. Additionally, thicker wafers appear to have an advantage in achieving superior flatness. Figure 9 shows the crack ratio as a function of wafer thickness in a 150 mm lapping process. Although there are many potential causes for cracking during lapping, after analyzing the data it is clear that wafer thickness plays an important role.
Wafer thickness has been demonstrated to have significant effects on shaping accuracy and manufacturing costs in wafer manufacturing and device processes. To avoid problems similar to those experienced with 300 mm wafers, determining the best wafer thickness for 450 mm is a critically important issue that must be determined by sufficient scientific and industrial research.
| Author Information |
| Tadashi Kanda is a manager at SUMCO’s Engineering Planning Department. After graduating from Hiroshima University’s Department of Physical Science, he worked on silicon crystal development. He received his D.Eng. from Fukuoka University. |
| Toshiyuki Fujiwara is a general manager in the Advanced Technology Development Department at the Production and Technology Division of SUMCO. He graduated from Osaka University, joined Sumitomo Metals in 1984, and transferred to SUMCO in 2001. |
| Kazushige Takaishi is a general manager in SUMCO’s Wafer Engineering Department. He manages the Wafer Engineering and Development Section. He received his M.S. from Tokyo Science University, joined Mitsubishi Metal Corp., and later moved to SUMCO. He has approximately 100 patents on silicon wafer processes. |
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