TSMC Begins Production of 40 nm Designs
TSMC said it is now in production of 40 nm designs for a wide variety of customers, ranging from Altera to Sun Microsystems. Although Qualcomm and others have used a TSMC 45 nm process, TSMC Vice President Di Ma said the company developed an IP platform and design support ecosystem for the 40 nm design rules.
David Lammers, News Editor -- Semiconductor International, 11/17/2008 7:00:00 AM
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In an industry where foundries often are reluctant to identify their customers, TSMC said early adopters of the 40 nm offering include Altera Corp. (San Jose), Advanced Micro Devices (AMD, Sunnyvale, Calif.), Broadcom Corp. (Irvine, Calif.), LSI Logic Corp. (Milpitas, Calif.), Marvell Semiconductor Inc. (Santa Clara, Calif.), Nvidia Corp. (Santa Clara, Calif.), NXP Semiconductors (Eindhoven, Netherlands), STMicroelectronics (Geneva), Sun Microsystems (Santa Clara, Calif.), and others.
The foundry has been making 45 nm products for customers such as Qualcomm Inc. (San Diego) beginning last year, said Di Ma, vice president of technical support at TSMC. However, the 40 nm platform is TSMC's main offering, rather than 45 nm. “The 40 nm technology comes with a platform of design enablers, an ecosystem of intellectual property and design support,” he said. “We didn’t do that kind of platform at 45 nm. We believe that 40 nm offers better value.”
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The 40G (general) process is aimed at high-performance sectors such as graphics, FPGAs and CPUs, and the 40LP (low power) process is targeted at markets such as broadband, wireless and application processors. “The real story of the 40 nm process is power. The 40G process, compared with the 65GP process, has a 45% active power savings,” Ma said. The 40G process delivers a 30% speed gain at a Vdd of 0.9 V, and a 60% performance improvement at a 1.0 V power supply. The 40LP transistor is optimized for lower leakage currents, and at 1.1 Vdd delivers a 43% leakage reduction compared with the 65LP process. Active power consumption is 51% less, and performance improves 7%, according to TSMC. The 40 nm process delivers a 2.35× gate density improvement over the 65 nm node. From an infrastructure perspective, Ma said the main difference between the 40 and 65 nm generations is the use of immersion 193 nm lithography.
TSMC’s roadmap includes an LPG technology that improves the performance of the 40LP process, according to Ma. Next year, the company will begin the process of offering a 32 nm technology with an oxynitride gate dielectric, and 2010 will mark the shift to 28 nm, including a high-performance process with a high-k/metal gate dielectric.
Although some analysts have said the foundries invest less in R&D than some of the IDMs, Ma said TSMC “is definitely making the investment to stay on a fast, two-year cycle.” In the past five years, he said, TSMC has spent >$10B on capacity expansions, and >$2B on R&D, with 1750 engineers employed to develop both the process technology and the intellectual property (IP) needed for a complete platform.
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