FSI Enters Single-Wafer Clean Market
FSI International (Chaska, Minn.) has made its single-wafer debut with its Orion cleaning system, which enables advanced wafer cleaning capabilities for such critical device structures as ultrashallow junctions, high-k/metal gates and metal capping layers. Innovative spray-bar and closed-chamber designs improve on competing single-wafer platforms, according to FSI's Scott Becker.
Aaron Hand, Executive Editor, Electronic Media -- Semiconductor International, 11/3/2008 10:22:00 AM
FSI International Inc. (Chaska, Minn.) has announced its entry into the single-wafer cleaning market with its Orion tool, noting the growing need for the single-wafer technology at 32 nm node and beyond critical device structures. Although FSI has previously relied on its batch spray technology to gain increased control over bath solutions, the toolmaker has answered the call for the further control single-wafer solutions can provide to reduce material loss during photoresist stripping after ultrashallow implants, and to eliminate material loss and galvanic corrosion in high-k/metal gates and copper interconnects with metal-containing capping layers.
“A couple years ago, our customers had come to us and asked if we had certain technologies that could be made available on a single-wafer platform, because they didn’t have them at the time for addressing what they saw as some upcoming significant issues for advanced nodes,” said Scott Becker, vice president of marketing and product management. FSI’s answer to this call is a single-wafer solution that takes a few extra steps in improving on existing single-wafer cleaning tools, Becker added, including a closed-chamber design, improved dispense system, and the use of FSI’s ViPR technology for higher reactivity rates.
Unlike open-chamber designs from single-wafer tool suppliers such as SEZ and DNS, the Orion closed-chamber design is better able to control the oxygen environment, Becker said, which enables the suppression of galvanic corrosion — a self-corrosion effect that’s caused by the electrochemical potential when two dissimilar metals are in contact with one another. To address this issue, DNS moves a shield plate over the chamber after chemical treatment. Although this approach helps to drive down the oxygen in the environment above the wafer, Becker said, it takes away the physical clearance for a moving dispense nozzle, instead relying on an unmoving center-point dispense nozzle that cannot use an energetic spray for improved cleaning. “So, in order to address the oxygen control issue, they’ve got to compromise on other cleaning capabilities.”
The Orion closed-chamber design resolves both issues by maintaining the closed chamber during the entire wafer processing, and using a spray bar that produces a linear array spray that provides greater wafer coverage and etch uniformity. “And the fact that we atomize our spray means that we’re going to use less chemicals and water,” Becker said. FSI can also energize the spray for improved chemical reaction time and rinsing efficiency, he added.
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| The spray bar integrated into the Orion closed-chamber design enables better etch uniformity, less chemical and water usage, improved defectivity without damage, and higher throughput. |
Besides the better control of oxygen in the closed environment, another advantage of the closed chamber is the ability to use very volatile, highly reactive chemistries such as the company’s ViPR technology, which significantly improves the effectiveness of stripping photoresists. FSI’s ViPR technology has been in manufacturing for a couple years on its Zeta batch spray tool, and has now been implemented on the Orion single-wafer platform as well. The chemistry is similar to a single-wafer chemistry, Becker said, but has an added ingredient that boosts the reactivity and temperature even higher — from <150°C for a wet bench to 160-180°C for other single-wafer solutions to ~220°C for the ViPR solution. This provides phenomenal increases in reactivity.
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| The Orion system has a closed chamber to provide oxygen control to eliminate metal etch and galvanic corrosion, and to enable to use of volatile, highly reactive process chemicals. |
The Orion tool targets three key areas at 32 nm and below: controlling material loss and damage in ultrashallow junctions, removing nickel platinum films selectively (especially challenging on SiGe), and achieving post-etch and post-ash cleaning without attacking metal gates or copper interconnect layers. “We see that these challenges are coming in as early as 32 nm, and no later than 22,” Becker said, adding that the time is now for when chipmakers need these solutions in order to be ready to start transferring 32 nm to manufacturing in the next year or two. “And right now the 32 nm integration schemes really aren’t finalized because they have unacceptable defectivity and higher cost than planned. And so part of what we’re bringing to 32 nm is to address these defectivity and cost issues.”
In a presentation at this year’s Ultra Clean Processing of Semiconductor Surfaces (UCPSS), Brian Kirkpatrick of Texas Instruments illustrated a growing concern with excessive material loss caused by ash and clean cycles at 32 nm and beyond. Four cycles of an ash and clean process shows a material loss of 1.4-2 nm in an example 65 nm gate. “That comes off the sides of the gate, which are typically going to be the spacer materials, as well as the active region, which is the active area where we’ve done our ion implantation,” Becker explained. “At 32 nm devices and logic, there’s going to be ~10-15 of these photoresist removal steps. So, if you scale it up, the total amount of material loss is quite excessive.” It’s commonly accepted, he said, that 32 nm logic devices will not tolerate the current combination of an ash step plus a clean step performed so many times.
With linewidths of ~24 nm, the tolerance to changing the widths of those lines becomes much more critical, Becker added. “If you change the width of the gate, you’re going to have phenomenal impact on the device performance.” Depth is also an issue, and changes in the shape of the electric field under the gate will also alter performance substantially.
The common practice for logic is to remove the bulk of the photoresist by putting it in an asher, and then following it by wet clean on a single-wafer wet clean tool, which would typically produce a material loss of ~5 Å, according to Becker. “If instead you decide not to ash and go with a high-temperature point-of-use chemistry in a single-wafer tool, you can drop that down very significantly to ~2.5 Å. So you can see why they really want to go to all-wet photoresist stripping.” With ViPR, because it’s much more reactive and hotter, material loss can go down to 0.2-0.5 Å for most implant conditions, he said, which already meets 22 nm technology requirements.
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| Stacked chambers surrounding a single robot enables the industry’s smallest eight-chamber cleaning system. |
