Logic Technologies Face Off at IEDM

At the International Electron Devices Meeting (IEDM) planned for Dec. 15-17 in San Francisco, IBM and its partners AMD and Freescale will present a thin SOI technology used to create a 22 nm functional SRAM with a cell size of 0.1 um2. Intel researchers will detail their 32 nm logic platform, which delivers drive currents of 1.55 mA/um for the NMOS and 1.21 mA/um for the PMOS transistors.

David Lammers, News Editor -- Semiconductor International, 10/28/2008 10:07:00 AM

Intel Corp. researchers will discuss the company’s 32 nm platform in a late paper submitted to the 2008 International Electron Devices Meeting (IEDM), and describe a record-performance pFET based on indium antimony (InSb). IBM researchers will present a 22 nm SRAM test chip at IEDM, while several other logic vendors will detail their most advanced process technologies.

Intel is saying that its 32 nm technology has the highest drive currents reported to date for NMOS (1.55 mA/µm) and PMOS (1.21 mA/µm) transistors. The company created a 291 Mb SRAM test vehicle with nearly 2 billion transistors. The SRAM array density is 4.2 Mb/mm², and the SRAM cell size is 0.171 µm², about half the cell size of the Intel 45 nm SRAM.

At the 45 nm node, Intel introduced a replacement metal gate solution with sharply reduced leakage current. The second-generation high-k/metal gate technology used at the 32 nm generation delivers gate length scaling and <1 nm effective oxide thickness (EOT), according to an abstract. The 32 nm test chip operated at 3.8 GHz at 1.1 V, which Intel said supports excellent performance for low-voltage applications.

IBM and its partners used a thin SOI technology for a 22 nm SRAM.

The Intel late paper will be presented at the end of session 27 on Wednesday morning (Dec. 17). That session includes a 22 nm technology presented by IBM’s T.J. Watson Research Center, along with researchers from Advanced Micro Devices Inc. (AMD, Sunnyvale, Calif.) and Freescale Semiconductor Corp. (Austin, Texas). The IBM-AMD-Freescale team will present a fully functional 6T-SRAM cell with a bit cell size of 0.1 µm², which IBM says is 30% smaller than the smallest SRAM reported thus far. The gate pitch of the 22 nm technology is 90 nm. The team used a double-exposure, double-etch technique to create a 35 nm gate length, according to the paper’s abstract.

The same Wednesday morning session on advanced CMOS logic includes a paper from Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC, Hsinchu, Taiwan) describing a 32 nm gate-first high-k/metal gate technology. The paper’s abstract claims record NMOS and PMOS drive currents at 1 V operation of 1340/940 µA/µm (n/p) at an I_off of 100 nA/µm. The TSMC team created a 2 Mb functional SRAM test vehicle.

Also, a combined team of researchers from Toshiba Corp. (Tokyo) and NEC Electronics Corp. (Tokyo) will present a 40 nm low-power technology with a logic density of 2.1 million gates/mm². Using a variety of techniques to lower the power consumption for logic and RF devices, the team claims a 50% power improvement over the best-reported system-on-a-chip (SoC) process for mobile applications.

InSb delivers record pFET

Intel researchers also will present a III-V p-channel quantum-well FET using a compressively strained InSb quantum-well structure. The device achieves a cut-off frequency (fT) of 140 GHz at a gate length of 40 nm and a supply voltage of 0.5 V. Although Intel is claiming that is the highest fT reported to date for a III-V p-channel FET, it still lags the fastest III-V n-channel FETs, which exceed 600 GHz. Compared with silicon devices, the InSb pFET device exhibits ~10× lower power dissipation for equivalent performance, or a ~2× improvement in speed for the same power dissipation.

Mike Mayberry, director of components research at Intel, said the goal is to build compound semiconductor devices on silicon substrates, taking advantage of the larger silicon wafers and equipment infrastructure. Although the III-V transistors “run fast and switch fast, they don’t turn off very well,” he said.

It is proving difficult to grow an oxide for III-V devices, Mayberry said. Intel and its supporting research partners at several universities are seeking a suitable high-k gate dielectric and an appropriate cleaning technology. “There are lots of problems due to the mix of surfaces there,” he said. “The thought is that if we can do high-k on silicon using ALD deposition, then we can do something similar with III-Vs.”

The other major challenge is that for most III-V materials, the performance disparity between the n-channel and p-channel devices is large. The Intel team also plans to build enhancement devices. “Most of the existing work is based on depletion-mode devices where you apply a voltage to shut them off. Power efficiency demands that those devices be normally off,” Mayberry said. “Another challenge is that most of these devices are pretty big. We need to make them small enough to compete with silicon transistor densities.”

Ideally, Intel would like to achieve a 3:1 or smaller ratio between the performance of the n-channel and p-channel III-V transistors, which would require strain techniques for the p-channel devices.

Although germanium channels are being studied, and GaAs transistors are fairly well understood, Mayberry said, “If we integrate a difficult material, GaAs may not be the one to go first. The reason we are working with InSb is that it has the highest mobility. If we are going to do all of the work we want to get the maximum gain.”

The 54th IEDM is scheduled for Dec. 15-17 in San Francisco, with two day-long short courses set for Dec. 14 on 22 nm CMOS and “More Than Moore” technologies.

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