Despite Losses, Toshiba to Continue Aggressive Investments
In a keynote speech at the ISMI Manufacturing Symposium, Toshiba executive Masakazu Kakumu said the company plans to invest $10B in its chip operations over 2008-2010. He outlined a series of wafer processing throughput improvements to double investment efficiency at the company's wafer fabs.
David Lammers, News Editor -- Semiconductor International, 10/22/2008 9:49:00 AM
Toshiba Corp. plans to invest ¥367 billion ($3.7B) in its semiconductor operations in fiscal 2008, despite expected operating losses of ¥65 billion ($650M) this year caused by the memory slump and weak global economy. Over the 2008-2010 three-year period, Toshiba expects to invest ¥1 trillion ($10B), according to Masakazu Kakumu, vice president of Toshiba’s system LSI division.
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| Masakazu Kakumu, vice president, Toshiba Corp. |
“Our aim is to be No. 1 in memory production,” Kakumu said. “Despite the severe economy and memory pricing, to meet demand in 2010 we will invest aggressively and continuously to increase capacity in the memory division.”
To cut memory production costs, Toshiba has started closing its older 200 mm lines at Yokkaichi in central Japan and moving the equipment to its discrete logic fabs, upgrading the Oita discretes fab on the southern island of Kyushu from 150 to 200 mm wafers. The main NAND flash fabs are being upgrade to 43 nm production starting this year, with plans calling for 90% of memory production to be at the advanced linewidth by March 2009, Kakumu said. The Yokkaichi Fab 3 is at 150,000 wpm now, and Yokkaichi Fab 4 will ramp to an even higher production level by 2010, he said. Fabs 5 and 6 are planned for Yokkaichi and Iwate, in northern Japan, he said.
Asked about Toshiba’s stance toward an eventual 450 mm wafer transition, Kakumu declined comment.
On the logic side, Toshiba is now the owner of the former Sony logic fab in Nagasaki. Kakumu said Toshiba’s 40 nm logic process is in pilot production now, with a graphics engine aimed at the PlayStation 3 as the first product to move to 40 nm at the Nagasaki and Oita logic fabs. Asked about its plans for high-k/metal gate integration, Kakumu said, “There is a possibility we may introduce high-k into our low-power 40 nm process in the future.” As a member of the IBM-led Fishkill Alliance, it will use the alliance’s 32 nm process, including high-k/metal gate, “adding differentiation, some slight changes of our own.” Also, Toshiba and NEC Electronics will cooperate on CMOS integration issues at the 32 nm node, he added.
Kakumu outlined a series of steps Toshiba plans over the next few years to double its fab productivity while reducing its carbon footprint and gas emissions. “Our view is that Toshiba will require a steep ramp of its mass-production lines and that will involve productivity and environmental improvements. We have a next-generation factory plan that will double our investment efficiency,” he told several hundred attendees at the ISMI Manufacturing Symposium. The goal is a production flow control system, with a next-generation automated material handling system (AMHS), advanced process control (APC), and feed-forward defect detection.
The AMHS will include a real-time dispatch system, an overhead hoist transfer and overhead buffer, and a carousel lifter.
The APC system will feature wafer run-to-run controls, and early detection of yield-limiting steps. A process feed-forward system, for example, will measure a die’s poly gate length and adjust the ion implant dosage accordingly, he said. “We have an APC approach to virtual metrology that will monitor such things as the process RF power in the equipment. Based on those measurements, the process conditions will be adjusted so we can have tight controls. If problems are detected by electrical testing, in the past we could have yield losses stretching out for several weeks. What we plan is defect detection after each process module, with a higher level of sensitivity of defect detection.”
A statistical model is being developed that will achieve “the optimum number of inspections so we can get the right trade-off between yield loss and inspection costs,” Kakumu said.
Also, Toshiba is developing a defect criticality index (DCI) that will measure the degree that defects contribute to yield loss as a function of defect size. A hot spot inspection die-to-database system is being implemented that identifies lithographic hot spots before volume wafer fabrication, he said.
On the energy and environmental fronts, Toshiba is asking its equipment suppliers to standardize on certain energy saving techniques. Similar steps are underway to save on the energy consumed by facilities. “We are studying the environment of our cleanrooms, coming up with new lighting systems, reduction of cleanroom gas emissions, and methods to filter recycled water,” he said.
