IMEC Has Air Gaps in Post-22 nm Roadmap for Interconnects

Though copper will clearly remain the interconnect material of choice, there may be some material changes in the barriers and capping layers after the 22 nm node, said Rudi Cartuyvels, director of interconnect, packaging and system integration, at IMEC's annual research review meeting. To achieve k<2.0, air gaps must be employed

Laura Peters, Editor-in-Chief -- Semiconductor International, 10/21/2008 9:50:00 AM

Though copper will clearly remain the interconnect material of choice, there may be some material changes in the barriers and capping layers after the 22 nm node. At the recent IMEC research review meeting, Rudi Cartuyvels, director of interconnect, packaging and system integration, provided an interconnect roadmap to reflect these and other possible changes.

The low-k material is moving from porous SiOC-based CVD materials to air gap approaches to attain k values of <2.3. The ultimate low-k values can be attained by using air gaps (k=1). Cartuyvels presented a process flow that used a porogen layer and porous oxide-like hard mask, which is patterned and filled with copper prior to porogen removal using a UV cure. The approach is simpler than others that have been proposed previously because it does not require additional lithography and etch steps, and multilevel air gaps can be achieved in one step. Using a 15% porosity hard mask, an experimental k~2.2 was obtained. With a 39% porosity cap, k~1.7 was achieved.

To lower the k value of the dielectric cap, IMEC projects a transition from today’s SiC/SiCN/SiCO module to a CuSiN/CuGeN/MnO module. If and when the current iPVD TaN/Ta barrier runs out of steam, alternative copper barrier chemistries such as ruthenium alloys and self-forming barriers could come into play. The thin copper seed, either pure copper or a copper alloy, could be replaced by a ruthenium alloy or an electroless self-aligned metal.

The need to reduce damage to ultralow-k materials is encouraging a move to metal hard mask patterning, or even double hard mask patterning, so that only the low-k etch and not the resist strip, interacts with the low-k material.

To achieve finer pitch and CD scaling at metal 1, double patterning sequences are being used. IMEC developed 32 and 22 nm node test vehicles with Black Diamond II low-k material and single-damascene patterning to investigate the reliability of these scaled structures. The single-damascene 30 nm CD uniformity after lithography was 2.5 nm (3σ) and 2.6 nm after metal hard mask etch (3σ). Final linewidth roughness (LWR) was 5.0 nm. IMEC determined that line edge roughness (LER) significantly impacts time-dependent dielectric breakdown (TDDB). At 32 nm, there is ~4× lifetime reduction if the 3σ LER = 7.3 nm (Figure). Cartuyvels pointed out that LER can be reduced by using a spacer-defined approach to double patterning, but he said this approach is more difficult to implement with dual-damascene schemes.

The impact of line edge roughness on time-dependent dielectric breakdown, a problem at 32 nm dimensions, is expected to get worse at 22 and 16 nm nodes.

IMEC’s tests on a self-forming manganese-rich copper barrier are so far encouraging. The CuMn (60 nm) is sputtered, and after copper fill, the MnSiO barrier self-forms during the anneal. The measured TDDB proved to be comparable to that of a conventional Ta(N)Ta barrier.

IMEC’s initial testing of a self-aligned CuGeN capping process showed a 4-8× improvement in electromigration lifetime with only moderate increase in sheet resistance. The film is formed by a germane and ammonia (GeH₄/NH₃) soak, followed by an ammonia plasma.

Finally, IMEC continues its work on copper contact, which must have sufficient barrier material near the silicide to prevent device failure. IMEC has demonstrated 50 nm copper contacts. First electrical results show the contact resistance values for copper at the 32 and 22 nm nodes are comparable with the values for tungsten contacts at the 65 nm node.