Interposers Play a Key Role in 3-D ICs
Participants at the Jisso Forum 2008, held recently near Tokyo, emphasized the important role that interposers will continue to play as 3-D interconnects using through silicon vias become more prominent. A Renesas study compared package thicknesses of a conventional flip-chip and an interposer-enabled memory-logic 3-D stack.
Kenji Tsuda, Asia Contributing Editor -- Semiconductor International, 10/15/2008 9:07:00 AM
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3-D ICs align the pads of a memory chip with those of a logic chip, for example. Although the long-term goal is to create ICs using standardized pad size and location, those standards will be difficult to accomplish, experts said at the forum. In the interim, interposers with redistribution interconnect layers will connect chips with pads that have different locations and sizes.
Without an interposer, the electrode pads of both stacked IC chips would need to be exactly aligned, leading to reduced design freedom. If chip designers have to unify the pad layout and size, they may be forced to modify their designs, possibly compromising performance and functionality. Interposers allow the pads of both chips to interconnect through redistribution, in many cases by allowing the interposer’s front surface to accept the pad design of the memory chip, and its rear surface to accept the pad design for the logic IC.
At the Jisso Forum, Tokyo University Professor Takayasu Sakurai said that 3-D ICs often require a re-distribution layer to adjust the TSV location and material discrepancies. It is difficult to create TSVs in the same location on the memory and logic chips, he said. Although the use of interposers may lead to increased costs, TSVs can boost performance by 20-30% and reduce power consumption by 30-40%, noted Nobuaki Miyakawa, director of the Honda Research Institute.
Takashi Kikuchi, a senior engineer at Renesas Technology Corp. (Tokyo), said thinner ICs are a major driver of TSV adoption. Renesas compared a 3-D IC with a TSV and interposer to a conventional flip-chip with wire-bonding. The conventional IC measured 1.25 mm tall, and a newly developed TSV and interposer IC was 0.6 mm. In both cases, the measurements included the height of the solder balls.
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| A Renesas Technology study compared a TSV-connected chip stack with an interposer (right), measuring 0.6 mm, with a conventional flip-chip combination (left). |
The Renesas conventional system-in-package (SiP) was a wire-bonded microcontroller on a flip-chip SDRAM on a six-layer substrate, encapsulated with a plastic resin. The newly developed SiP has an SDRAM chip connected by TSVs to the bottom microcontroller, which is connected to a two-layer substrate. The improved height is partly due to a reduced interconnect layer of the substrate, according to Kikuchi.
