Packaging News: Scaling Test Sockets, 3-D Consortium

Test Socket Industry Faces Issues Scaling Below 0.4 mm Pitch

The test socket industry is encountering electrical and mechanical issues as package pitch sizes shrink below 0.4 mm. The major challenges include increased package size, which means more I/O to test, and RF testing requirements that would introduce signal integrity issues. To scale to tighter pitches, it appears that new materials, designs and contacting technologies are necessary for test sockets.

As a point of reference, test sockets contacts are now smaller than the lead found in a mechanical pencil, which is typically 0.5 mm. Spring pins used in 0.4 mm test sockets are about half that diameter. Even more amazing is that these spring pins are assembled by hand.

Right now, the test socket market is being driven at a much faster pace than in the past from mechanical and electrical perspectives — in terms of form factor, pitch, high speed and RF drivers. “Mechanical packages are shrinking rapidly as the electrical needs are increasing much faster, which puts tremendous pressure on test socket suppliers to develop new technologies,” noted Ila Pal, engineering manager at Antares Advanced Test Technologies (Vancouver, Wash.). “Shrinking from 1.0 mm pitch to 0.5 mm was easily scalable, but that's not the case moving from 0.5 mm down to 0.3 or 0.2 mm pitch. That's one of the biggest challenges facing the test socket industry right now — we need to look at new technologies.”

The trend toward tighter pitches is one Aries Electronics Inc. (Bristol, Pa.) is also responding to. Its customers are requesting test sockets not only for ball grid array (BGA) devices, but also other surface-mount-type devices, on increasingly smaller pitches. “We offer five different outer shell housings, with pin pitch options ranging from 0.8 mm to 0.3 mm (Figure). These housings consist of a frame for the base, hood and pressure pad — all with different closing mechanisms. All that's missing are the 'guts' of the socket — the middle part designed to accommodate the specific device for the customer,” said Frank Folmsbee, Aries' national sales manager. This middle part consists of an interposer set, which is drilled to the footprint of the device, then a male probe and the female spring are fitted into the holes.

The spring-probe outer shell housings are offered in a variety of pitches. (Source: Aries Electronics Inc.)

Although demand for a 0.2 mm pitch hasn't begun yet, 0.4 mm is becoming increasingly common. “We have a robust solution for 0.4 mm, but we can't scale that same technology down to 0.3 mm and expect the same performance as 0.5 mm. Our 0.25 mm solution is in the prototype stage,” Pal said.

One of the greatest challenges associated with sub-0.4 mm pitches becoming more mainstream is the growing package size, according to James Forster, CTO at Antares. “It was originally thought that packaging sizes for 0.4 mm would be 12 or 14 mm square, but now they're going up to 24-25 mm square,” he explained. “This means a lot of I/O in a very small space, which creates challenges for test and burn-in socket suppliers. As the pitch gets finer, the available space for the springs and contact tips is less. One solution that's gaining ground is the use of elastomers with Z-axis conductivity. Some are not pitch-specific and there is no pre-load, meaning that the mechanical strength to hold the contacts is a non-issue with elastomer sockets. There is, however, some concern about the reliability and lifespan of elastomers in a production handler, as well as concerns about the materials at higher test temperatures.”

Another challenge is that the move to 0.2 mm will likely require new contacting technologies. There are methods to contact at 0.2 mm, but not at the expected frequencies or cost point, Forster pointed out. “For example, flip-chip devices with pitches of 0.2 mm are routinely tested today. I think we're going to see a merging of the kinds of technologies used at probe with the kinds of technologies that are used for test,” he added. “How we'll see those come together for wafer-scale and wafer-level chip-scale packages is uncertain. But some companies who build membrane probes are supplying solutions for test at 0.2 mm. The problem is that the cost on a per-socket basis is orders of magnitude too high.”

Because of the European Union's RoHS lead-free regulation, materials are now an issue for test sockets. “A challenge here is that package manufacturers optimized lead-free from an assembly perspective, which is what they should have done,” Pal explained. “But the major step that happens prior to assembly is testing the packages with test sockets. The packages aren't optimized for test, so we're encountering lots of issues here.”

Packages with high pin counts (4000-5000) are also an issue because the existing test socket material isn't able to withstand the force and stress being applied, according to Pal. “It's a big challenge for the test socket and is driving materials suppliers to do innovative things such as embedding nanotubes inside their materials to add strength,” he said. “Obviously, a thin socket is desirable, but it needs to be able to withstand 4000-5000 pins without deflecting. For a plastic to do that, more innovation will be required.”

Forster believes signal integrity issues are imminent. “We'll see some coaxial-type sockets or sockets that use innovative ways to bring in some of these high-frequency signals,” he elaborated. “We've seen new packaging types, and testing of some PoPs requires sockets that can contact not only the bottom of the package, but also the top. That's challenging us a bit.”

Last, but not least, power problems emerge as the I/O pitch decreases on a socket, the chip voltage decreases and total functionality increases. “There are two opposing requirements — smaller pitch and increasing power,” Forster said, noting that the cross-sectional area of the contact is smaller, but it must carry more current. “The only way to carry more current is to increase that cross-sectional area, not decrease it. Now we get into the problem of I2R heating, the additional thermal load due to self-heating of the contact, and that's a challenge. To address this, chip designers are putting in more pins to carry the current in and out. And the socket people are looking at different ways of doing what we do today. If it's a peripheral leaded device, we can easily go to 0.4 mm. And because we have the space around the edge of the package, we have the benefit of being able to make the contact fairly substantial. With an area array package, such as a BGA or a multi-row QFN, getting all that power in can be a challenge.”

Georgia Tech, Partners Launch 3-D Consortium

Georgia Institute of Technology’s (Atlanta) Packaging Research Center (PRC), along with academia partners at Fraunhofer IZM (Berlin) and Korea’s Advanced Institute of Science and Technology (Daedeok Science Town, Korea), will officially launch the 3-D All Silicon System Module (3DASSM) consortium in October.

The consortium’s long-term vision is a complete system that will be entirely silicon-based, according to 3DASSM program manager Ritwik Chatterjee. This includes all components, system boards, ICs and the package itself. Initially, the consortium plans to work on projects in five key categories: low-cost through-silicon vias (TSVs) and stack bonding; electrical design and test; packages with fine-line wiring; embedded active and passive components; and system interconnections. More than 20 research projects have been proposed.

“Our 3DASSM consortium isn’t limited to merely TSVs and the stacking of ICs,” pointed out Rao R. Tummala, director of the PRC. “It’s about ultraminiaturization and ultrafunctionality at the lowest-cost, all-system level — in contrast to what’s being done with system-in-package [SiP] at module level and system-on-chip [SoC] at the IC level. We’re developing an all-silicon 3-D system with seamless integration of ICs, packages and boards.” Tummala said the use of a silicon wafer as a board, with seamless integration of ICs, packages and embedded thin-film components, enabled by TSVs, will bring about a disruptive set of system characteristics.

One of the consortium’s first projects seeks to address the industry problem of high-cost, low-reliability TSVs. Researchers will look at new fabrication methods for high-density, low-cost TSVs, new structures that improve thermomechanical reliability, novel low-cost solder and adhesive stack bonding methods — research that’s expected to result in a 3-D stack bonding test vehicle and a silicon package test vehicle to demonstrate the improved performance, reliability and manufacturability of the technologies developed.

Electrical design and test work will reach beyond 3-D, but starts with low-cost 3-D. This includes electrical design and test of TSV, 3-D stacks, SiP and ball grid array (BGA) packages and wafer system modules. Low signal switching noise, novel equalization methods and EDA tools for electrical and thermal co-design will be investigated.

In terms of silicon packages for SiP and BGAs, 3DASSM is focusing on double-sided silicon substrates enabled by TSV, replacing current organic SiP and processor substrates with improved I/Os, wiring, planarity, thermal and electrical performance, reliability and cost.

In the system interconnections category, the goal is to solve the mismatch challenge between silicon packages and organic boards by a variety of rigid and compliant interconnections.

To ensure a clear path to commercialization, the consortium will bring other research companies and supply chain companies on board, Chatterjee said.