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Industry News: 3-D Startup, Zelenograd Fab, Photonic Beetle, 22 nm SRAM

Staff -- Semiconductor International, 10/1/2008

3-D Startup Is Ahead of Its Time

As the 3-D integration infrastructure evolves, it is clear that low-cost, reliable bonding technology is required for 3-D IC integration to become mainstream. Although several options exist, the industry has generally accepted that metal-metal bonding is favored because it forms both the mechanical and electrical bond at the same time. It is also generally accepted that via-first technologies (where the vias are fabricated in the fabs, whether FEOL or BEOL) will be significantly easier to manufacture than the alternative via-last technologies. An issue that remains is throughput. Direct copper-copper bonding involves bonding at 350-400°C for 30+ minutes under pressure, requiring commercial aligner/bonder tools to have multiple bonding heads per tool to achieve reasonable throughput. The industry is looking for solutions with lower cost of ownership (CoO).

Ziptronix’s DBI process: die-to-wafer 3-D integration by pick-and-place. (Source: Ziptronix)
Ziptronix’s DBI process: die-to-wafer 3-D integration by pick-and-place. (Source: Ziptronix)
Ziptronix spun out from RTI International (Raleigh, N.C.) in late 2000 to commercialize wafer and die bonding technology. The startup’s extensive patent portfolio is centered around its ZiBond and Direct Bond Interconnect (DBI) technologies. Direct bonding processes require extremely smooth (<0.5 nm RMS) and clean surfaces, which are readily achieved with standard chemical mechanical planarization (CMP). The DBI process is applicable to both aluminum and copper interconnect chips, and both face-to-face and back-to face wafer-to-wafer (W2W) or chip-to-wafer (C2W) bonding. Having a capping of DBI metal over the copper reportedly improves planarity of the oxide/metal interface after CMP, which results in better bonding. In the case of copper, the DBI cap eliminates the dishing that would normally occur in the soft copper metal in the presence of the hard oxide during CMP. Ziptronix then uses one of several patented variations of ZiBond technology to activate and terminate the oxide surface. This chemical modification significantly lowers the temperature required to achieve a strong, reliable bond.

“In one of our embodiments, a DBI metal, nickel, is plated on top of exposed tungsten or copper TSV [through-silicon via] after thinning [back side], or on top of an aluminum or copper BEOL [front side], then covered with an interlevel dielectric and CMP’d to expose the nickel,” said Paul Enquist, Ziptronix CTO. “Likewise, one embodiment of our ZiBond IP simply requires a quick plasma treatment followed by an aqueous ammonium hydroxide rinse. … These processes can be easily implemented at CMOS wafer foundries, IDMs or OSATs.”

“The direct bond is initiated in a few seconds with a standard pick-and-place tool [W2W or D2W],” Enquist added. “Wafers are subsequently batched and heated at ~300°C to complete the electrical interconnection at the aligned Ni-Ni interface. Since the activated and terminated oxide layers are bonded together with high strength, the Ni-Ni interface is subject to sufficient internal pressure so that when the nickel expands at elevated temperature, a reliable metallic bond results. The combination of a low-capex pick-and-place tool and high wafer throughput lead to lower CoO for the entire process.”

Ziptronix has electrical and reliability data on structures containing 1 million bonded pairs on 8 µm pitch that show interface resistances <0.5 Ω/µm2, and have passed 1000 thermal cycles (-65 to 175°C) and HAST testing. Interconnect pitches of 1.5 µm have also been demonstrated, Enquist said, and submicron pitches are possible with improved alignment tools.

Dan Donabedian, Ziptronix CEO, reported interest from “several major foundries who have announced that they will be supplying TSVs as part of their fab services in the future, and several IDMs and OSATs who say they will be offering bonding services very soon.” Interest is reportedly also strong from “CMOS image sensor providers who are moving to backside illumination and require low-temp and low-CoO oxide bonding technology to make this technology economically viable.”

“The broad and fundamental nature of our patent portfolio leads us to believe that any use of an oxide low-temperature bonding process is highly likely to be covered by one or more of our patents,” Donabedian said. “This company was clearly spun out too early; we were too far ahead of the 3-D integration infrastructure. …It appears that our time has now come, and we aim to take advantage of this current situation.”

Phil Garrou, Editorial Advisor


Sitronics Plans 300 mm Fab at Zelenograd

Sitronics Inc. (Moscow) will receive more than a billion dollars from a Russian governmental investment fund to build a 300 mm wafer fab at Zelenograd, near Moscow, according to a government ruling signed by Prime Minister Vladimir Putin.

Sitronics reportedly will build a 300 mm fab near Moscow, using licensed 65 and 45 nm technology. (Source: Sitronics)
Sitronics reportedly will build a 300 mm fab near Moscow, using licensed 65 and 45 nm technology. (Source: Sitronics)
The new fab will use licensed 65 and 45 nm technology, chosen from among IBM Corp. (Armonk, N.Y.), Intel Corp. (Santa Clara, Calif.) and STMicroelectronics (Geneva), Sitronics president Sergei Aslanyan told Russian reporters. The 65 nm technology will be used to make ICs for digital televisions and global positioning systems, he said.

In addition to the competition for a process technology provider, a bidding process will be established for the equipment and fab construction vendors, Sitronics spokeswoman Irina Lanina told the Russian business daily Vedomosti.

Sitronics, which operates telecom and microelectronics production facilities in Russia and other former members of the Soviet Union, will invest 31.5 billion rubles (~$1.25B) in Sitronics Nanotechnology over the next few years, the reports said. The total project will cost 58.43 billion rubles ($2.32B), of which the government investment fund will provide 26.92 billion rubles ($1.07B).

Sitronics has an existing licensing arrangement with STMicro for 0.18 µm technology, which Sitronics has used since 2007 to make chips for passports, cellphone SIM cards, transportation debit cards, and RFID tags. The company will move to 130 nm technology this year, and plans to begin making 90 nm chips in 2009, processing ~10,000 200 mm wafers per month, the reports said.

With a staff of >10,000, Sitronics produces telecom equipment and software, ICs and other components, and consumer electronics. Sitronics Microelectronics operates production fabs in the Ukraine and in Zelenograd, Russia.

David Lammers, News Editor


‘Photonic Beetle’ Points to Ultrafast Computing

The proverb admonishes, “Look to the ant, thou sluggard, consider her ways and be wise.” The same sentiment can be applied to another member of the Insecta class, a green iridescent Brazilian beetle with the unwieldy moniker of Lamprocyphus augustus. Just by doing what comes naturally, this inch-long weevil has accomplished a task that to date has eluded the Hominidae class's best researchers: the evolution of a structure considered as the ideal architecture for the long-sought-after photonic crystal.

This gaudy-looking beetle managed to do what researchers could not: evolve a crystal structure in its scales considered as ideal for photonic crystals, which will be crucial for future ultrafast optical computers. (Source: J. Galusha, University of Utah)
This gaudy-looking beetle managed to do what researchers could not: evolve a crystal structure in its scales considered as ideal for photonic crystals, which will be crucial for future ultrafast optical computers. (Source: J. Galusha, University of Utah)
To produce ultrafast optical computers, it is first necessary to produce an ideal photonic crystal that will enable exacting manipulation of light. Currently, light in near-infrared and visible wavelengths carries data and communications through fiber-optic cables, but this photonic information must be converted back to electrons before it can be processed by a computer.

“Photonic crystals are a completely new class of optical materials that enable the manipulation of light in non-classic ways,” explained Michael Bartl, assistant professor of chemistry and adjunct professor of physics at the University of Utah (Salt Lake City). “Some colors [wavelengths] of light can pass through such a crystal at various speeds, while others are reflected as if the crystal were acting as a mirror.”

Bartl and his group, which includes researchers from Brigham Young University (BYU, Provo, Utah), have been trying to make 3-D photonic crystals with a full photonic bandgap, a concept similar to that of an electronic bandgap, to keep light of a specific frequency from penetrating the crystal. “Proven research in physics demonstrates that if you have such a material, it'll give you the potential for things like increasing the efficiency of photovoltaic cells, to very low-threshold lasing [light amplification], as well as for establishing optical qbits, which are the cornerstone of some optical computing,” Bartl said.

The Utah researchers had been trying to make different structures with optimized, high-quality architectures. “We struggled,” Bartl said. “Lithography is limited when it comes to 3-D, 100 nm feature size structures. If you use self-assembly techniques with self-assembled silica spheres to produce a photonic opal, you end up with a closed structure; you cannot open the full photonic bandgap with a photonic opal, which is what we are interested in.”

The ideal, so-called “champion” photonic crystal was described in 1990. This Holy Grail is a crystal with the same structure as the lattice of carbon atoms in diamond. However, because of its atomic density, a diamond cannot manipulate visible light or be used as a photonic crystal. However, a diamond-like structure made of the right material would provide a large photonic bandgap, preventing the propagation of light in certain wavelengths. This would enable optical circuits capable of manipulating visible light.

So where does the green arthropod come in? Lauren Richey, now a BYU student, had done a high school science fair project on iridescence in biology. A BYU group was helping her then, and they got her the bug. “The beetle was interesting because it was iridescent regardless of the viewing angle,” Bartl recalled. “We wondered what 3-D structure could produce such unique optical properties.”

The Utah team's preliminary electron-microscope investigation revealed that the insect's scales did not have the structure typical of artificial photonic crystals. Using a focused ion beam, 150 cross-sections were made of one of the beetle's scales in a process akin to tomography, and then digitally put it back together using imaging software. They found that a single scale is not a continuous crystal, but includes some 200 pieces of chitin, each with the diamond crystal structure, but oriented in different directions, each reflecting a slightly different wavelength of green. “The scale material's structure had a champion architecture, but used chitin and air instead of the carbon atoms in diamond,” Bartl said. Next, the researchers applied optical studies and theories to predict the properties of the scales' structure, and their prediction matched reality — green iridescence in the 500-550 nm range.

“We're working to design a synthetic version of the beetle's photonic crystals, using the scale structures we discovered on it as a mold for the crystal,” Bartl said. “Although the biological structure is very nice, it has the disadvantage of being made out of chitin, which would not work in any technological application. We want the same structure, but made out of a semiconducting material with a high refractive index.”

The group is currently considering titanium dioxide. It is a wide-bandgap semiconductor transparent to visible light, meaning that it does not absorb photons, something that would result in data loss in a hypothetical optical computer. Another advantage is that the material also has a high dielectric constant and has already been used in things like photovoltaic cell electrodes.

Although the application of photonic crystals is just now beginning, there are many possible uses: as sensors in metrology devices, as light amplifiers to make photovoltaic cells more efficient, to capture light that catalyzes chemical reactions, and to generate small lasers to serve as light sources on optical chips.

The materials that would allow the creation of perfect photonic crystals to manipulate visible light do not yet exist, whether natural or synthetic. They will have to be developed. However, the researchers are presently preparing their results for publication, and appear quite pleased with what they will report.

Alexander E. Braun, Senior Editor


IBM Alliance Builds 22 nm SRAM Cell

IBM Corp. (Armonk, N.Y.) and its development partners — Advanced Micro Devices (AMD, Sunnyvale, Calif.), Freescale Semiconductor Inc. (Austin, Texas), STMicroelectronics (Geneva), Toshiba Corp. (Tokyo) and the College of Nanoscale Science and Engineering (CNSE, Albany, N.Y.) — said they have developed the first working SRAM at the 22 nm technology generation.

IBM's 22 nm SRAM cell has
            an area of 0.1 µm2. (Source: IBM)
IBM's 22 nm SRAM cell has an area of 0.1 µm2. (Source: IBM)
The six-transistor SRAM cell has an area of 0.1 µm2. IBM said the researchers optimized the SRAM cell design and circuit layout to improve stability. The SRAM cell includes a high-k/metal gate stack, a 25 nm gate length, thin spacers, novel co-implants, advanced activation techniques, extremely thin silicide, and damascene copper contacts.

The researchers built the cell at CNSE, where IBM and its partners perform much of their semiconductor research. IBM spokesman Ron Favali said he could provide few additional details, noting that the brief announcement of the working cell precedes a paper to be presented at the IEEE International Electron Devices Meeting (IEDM), planned for Dec. 15-17 in San Francisco.

The announcement comes less than a year after IBM announced its 32 nm SRAM with high-k/metal gate technology.

Staff

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