De Geus Highlights Photomask Simulation Challenge

Synopsys CEO Aart de Geus described the need for more powerful simulation engines and other simulation challenges facing the mask industry, in a keynote presentation at the 28th Photomask Technology conference going on this week in Monterey, Calif. Other opening-day speakers detailed a Sematech mask industry survey and the stiff challenges posed by double-patterning lithography.

Alexander E. Braun, Senior Editor -- Semiconductor International, 10/8/2008 9:28:00 AM

The 28th Photomask Technology conference opened yesterday in Monterey, Calif., with a keynote presentation by Aart de Geus, chairman and CEO of Synopsys Inc. (Mountain View, Calif.), who looked at the importance of more powerful simulation engines.

“There has been an evolutionary process, centered on lithography, that has gone from just defining devices to layout, mask, chip, and then manufacturing,” de Geus said, noting that the process is increasingly simulation-driven. “On the TCAD side, we’ve seen it go from 2-D to 3-D simulation, to essentially dynamic simulations where you can track waveforms.”

As device technology progresses, mask complexity grows. (Source: Synopsys)

De Geus predicted there will be a combination of simulation techniques that will combine with litho, and extend to manufacturing. He acknowledged that the challenge is to make this practical from a computational and manufacturing standpoint.

In mask shops, the manufacturing reality is not that simple. Increasingly, there is a need to simulate the actual patterns and wavelengths of light as they apply to photoresists — not a minor thing. “Today, we can do these kinds of calculations on a space of about 3 × 3 µm, which is quite remarkable,” de Geus said. “Doing it on complete chips will take an extraordinary amount of computing power. The challenge is how to translate this into actual electrical performance. If you assume that what is drawn is what will actually be on the chip, you’ll be disappointed.”

Modeling and simulation are needed to control all levels of the semiconductor process, including manufacturing. (Source: Synopsys)

In a sense, everything centers on simulation capability, and the key is whether the needed modeling and simulation can be made cheap and fast enough. “In the fab, simulation techniques will grow in importance as well. Eventually, modeling and simulation should produce a virtual manufacturing model, which could work itself backward into the design process to look at situations that may have negative results on the chip. In this landscape, the only way to bring everything together is by producing the correct models.”

Maskmakers increasingly depend on simulation engines to create production-worthy reticles. (Source: Synopsys)

Sematech mask survey results

Greg Hughes, a researcher at Sematech (Austin, Texas), presented results from this year’s Mask Industry Assessment, with survey responses from eight mask manufacturers. According to the information gathered, the market for photolithography tools, mask equipment, resist materials and masks is $13.1B, with masks alone accounting for $2.83B. Hughes observed that 56% of masks are at ground rules of 250 nm and above, 70% are at 180 nm and above, and 11.6% are below 90 nm, with logic accounting for 44% of all masks. He presented data to the effect that 74% are without optical proximity correction (OPC), and that 50% are written by laser, and 73% are made with wet etch processes. Phase-shift masks account for ~7.5% of the total shipped.

“The average yield for all masks is 93.8%,” he said, adding that 40.7% of masks are not repaired, and that hard defects account for 56.9% of the yield loss. “Mask maintenance is showing significant pellicle degradation rates for 193 nm, exceeding 248 nm by more than 15×,” Hughes said. The data indicates that the average incoming data file is 4.9 GB, and takes eight hours of preparation time and more than three hours to write.

Double patterning verification is challenging

In a presentation titled, “Printability Verification for Double-Patterning Technology,” G. Luk-Pat of Synopsys highlighted how recent work has focused on decomposing a design into two patterns. “After these patterns are subjected to retargeting, OPC, and other resolution enhancement techniques [RETs], it’s important to verify the printing of the combined patterns on the wafer,” he said, adding that verification can produce feedback to each RET step, particularly the decomposition tool, to the layout tools, and even to the designer.

Double patterning (DPT) is challenging when it comes to printability verification, because the resist target can be very different from the etch target; for instance, a trim etch can shrink the CD from 45 nm after resist to 30 nm after etch. Also, there are overlaps between the two patterns that produce problems absent from single-pattern imaging, such as sharp corners, pinching at the pattern junctions, and bridging between patterns. “Then there are process variations, such as misalignment between the two patterns, and twice as many dose, defocus and mask-bias dimensions,” Luk-Pat said, adding that DPT problems can be solved through OPC, decomposition or DPT-aware design.

Klaus Herold of Infineon (Milpitas, Calif.) presented “Single Exposure Is Still Alive: Gate Patterning at the 45-nm Technology Node.” He pointed out that, although immersion lithography has been in use for years, significantly increasing printability without a major increase in manufacturing costs, double patterning will raise costs because it requires a doubling of most of the steps, such as masks, exposure and etch.

Herold outlined some necessary steps to scale the single-patterning approach into the 45 nm node. “One of the most important was the introduction of a new pixel-based engine for OPC,” he said, adding, “Although we achieved excellent results with sparse OPC previously, tight control across chip line variations couldn’t be met at the 45 nm node. OPC recipes had to be reinvented because of the software architecture’s radical change.”

Although a microprocessor design can tolerate restrictive design rules, a foundry must offer the least burden possible to its fabless customers to enable them to scale to the next technology node. This requires the patterning process to support all the line and space combinations that are necessary. A key enabler for this, he said, is a separate process model in the data preparation flow for the correction of etch proximity effects.