Yale’s T.P. Ma Proposes Unipolar CMOS
Professor T.P Ma of Yale University has proposed a new type of CMOS, named Unipolar CMOS, that would use electrons in both channels. "All I am doing," Ma said, "is replacing the conventional p-channel by an n-channel transistor that has a negative threshold voltage." Ma, who won the IEEE Andrew Grove award in 2005, said Unipolar CMOS would gain a speed advantage by not using the slower holes as carriers. Density would improve by using a shared contact.
David Lammers, News Editor -- Semiconductor International, 10/8/2008 8:00:00 AM
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| T.P. Ma, Yale University |
The device is a dual-channel structure that would use electrons in both the front and back channels, taking advantage of the higher mobility of electrons compared with holes. At room temperature, holes in silicon have a mobility of 450 cm2/Vs, while electron mobility is 1500 cm2/Vs. For III-V channels such as GaInAs and InAs, the disparity between hole and electron mobility is more than an order of magnitude.
“It is a CMOS inverter, except with all n-channel performance, so we don’t need holes,” Ma said.
Listen to an audio interview with T.P. Ma (Runtime: 16:15)
NMOS was widely used until the early 1980s, but then was abandoned because of high standby power consumption due to one of the logic states drawing power at all times. Unipolar CMOS would have one channel on while the other channel is off, providing a CMOS-like switching with minimum standby power consumption.
The front and back channels are asymmetric, achieving front channel inversion and back channel inversion. The front inversion channel is in the on state when the drain and source are connected. If the back channel is inverted, the source and drain are not connected and no current flows. When the back inversion channel is on, the front channel is blocked by an insulator, or spacer, and will not drive current.
The technology relies on the front channel having a positive threshold voltage (Vt) relative to the source, while the other channel is controlled by a negative Vt. When the input is high, it turns on the front channel, while the back channel remains off and draws no current. If the Vt is low, or negative relative to the source, the back channel will be inverted while the front channel is off.
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| Unipolar CMOS replaces the conventional p-channel by an n-channel transistor that has a negative threshold voltage. (Source: T.P. Ma) |
“All I am doing,” Ma said, “is replacing the conventional p-channel by an n-channel transistor that has a negative threshold voltage.” The concept takes advantage of the front and back channel of a double-gate device, where the back-channel transistor replaces the p-channel transistor of the conventional CMOS inverter.
The device also can be made to work in accumulation mode. “Some semiconductors are more easily accumulated than inverted, and we can accommodate that,” Ma said.
Although the figure in this article uses an SOI structure to demonstrate the unipolar logic, the same concept can be readily adopted for a 3-D double-gate or finFET structure.
Ma said the idea came to him about a year ago when he was considering ways to move beyond silicon CMOS, which is facing the end of scaling. “The idea came to me because of the disparity in speeds between the p-channel and the n-channel, especially for III-V semiconductors,” he said.
Since then, he has developed simulations, and Yale has filed for a fundamental patent on the approach. The next step is to attract a company or consortium to build the device in silicon or III-V semiconductors.
Ma won the IEEE Andrew Grove Award in 2005 for his research in high-k dielectrics, and other contributions. Born in China and raised in Taiwan, he worked for several years at IBM Corp. after earning his doctorate at Yale in 1974, and then joined the faculty there in 1977. While the ultimate success of Unipolar CMOS remains to be seen, Ma said he is confident that he can convince senior management at IBM, Sematech or TSMC to commit the resources needed to build prototype Unipolar CMOS circuits.
Compared with carbon nanotubes or graphene-based semiconductors, Unipolar CMOS involves no special fabrication breakthroughs. Studies underway at Yale have simulated the devices in series or in parallel to make OR, NOR, AND and NAND logic, but in ways that Ma said can be simpler than in conventional CMOS.
“I call it Unipolar CMOS because, in the device architecture, one n-channel device has a positive threshold voltage, while another has a negative threshold voltage,” Ma said. “In that sense, it is very much like n-channel and p-channel CMOS, but in my design the negative threshold n-channel replaces the negative threshold p-channel. Once you have that, you can more or less follow the CMOS architecture.”
At the Sematech conference, Ma said Unipolar CMOS would be simpler to build than conventional CMOS, with a less-complex material set than leading-edge CMOS, which requires expensive strain techniques to speed up the pFETs.
Because the source and drain have the same polarity, they share a common contact, he said. Also, the devices could be built without p-well and n-well isolation, reducing the number of mask layers. “We don’t need shallow trench isolation, and we share the contact, whereas in regular CMOS we have to separate the n-channels and p-channels. So in addition to the higher mobility from using all electrons, there is a simplicity advantage. My estimate is that the density could improve substantially, perhaps by 2×.”
A smaller cell size also would contribute to performance, but Ma said the primary speed boost would come from using electrons in both transistors.
At the Sematech presentation, Ma recounted progress in creating NMOS transistors in III-V materials, including GaAs, InGaAs and others. One of the challenges with III-V transistors derives from the relatively poor performance of the p-channel devices. While the wide disparity in mobility between the electrons and holes is a problem for an all III-V technology, Unipolar CMOS would rely solely on the faster electrons.
“If I compare a logic circuit made of indium arsenide, it has an extremely high electron mobility of 40,000 cm2/Vs but only a 500 cm2/Vs hole mobility. With strain to boost up the p-type mobility 4× to 2000, that disparity is still a factor of 20. The result is a skinny n-channel and a 20× fatter p-channel. The area and layout is very inefficient.”
The imbalance has led Sematech and other research centers to work on heterogeneous CMOS, with a III-V layer epitaxially deposited n-channel and a germanium layer grown in the p-channel. Many semiconductor companies are well down the path of developing germanium or SiGe channels, to take advantage of the higher hole mobility in germanium compared with silicon.
The transition to III-V and/or germanium materials would be needed after silicon CMOS scaling ends in a decade or later. If Unipolar CMOS were to be deployed with an InGaAs n-channel technology, researchers could concentrate on development of a gate insulator and other parts of the n-channel III-V technology.
“P-channel enhancement with III-Vs is difficult,” Ma said. “We could give it up, and just work on the n-channel because with Unipolar CMOS we don’t need the p-channel.” Also, scaling could be relaxed, starting with perhaps 0.5 µm devices while still getting a performance advantage over 45 nm silicon CMOS.
Albert Chin, a professor at National Chiao-Tung University (Hsinchu, Taiwan) who heads up the process technology subcommittee of the upcoming International Electron Devices Meeting (IEDM), suggested that the industry should concentrate on a silicon version of Unipolar CMOS. “As we continue to scale down the current form of CMOS, the drive current doesn’t increase that much. That is why Professor Ma’s idea is so important. Improving the operating speed is why so many people are working on III-V technology, but III-Vs have so many problems, such as finding an oxide, defect density, and others. If this Unipolar CMOS works, then we won’t have the severe scaling issues with silicon. We can get rid of the PMOS transistors and switch much faster.”
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