Yield Learning Flow Provides Faster Production Ramp

In response to market demands, IC designers are required to create chips at smaller design nodes that include greater functionality with faster clock speeds using less power. In addition, production of these enhancements must happen in less time than the previous design to meet market windows. Once the design is taped out, the time-to-market pressure is on manufacturing and yield ramp. If the chip doesn’t ramp up fast enough in manufacturing to the expected yield, the product may be late to market and there won’t be enough chips to satisfy customer demand.

Simply put, yield is the percentage of customer-deliverable parts vs. all parts manufactured. But in reality, it’s a little more complicated. Yield refers to the number of good chips vs. the number of total chips produced, whereas “quality level” refers to the number of good parts shipped vs. the total number shipped. Yield is focused on during two manufacturing phases: at initial ramp and during mature manufacturing.

Yield ramp is how quickly a new design ramps up to the expected initial yield when it goes into manufacturing. Mature yield is the expected yield after it has been in production for some amount of time. A mature high-yielding part produces profit that can go back to the IC design company to fund the next project. A low-yielding part can cause a company to lose money and thus restrict the ability to fund new projects. So that’s why it’s important for a chip to reach high yield as quickly as possible — the profit potential.¹

Yield-limiting issues typically fall into one of two categories: systematic defects or random defects. At 65 nm and below, random defects typically contribute <45% of yield loss. The rest of the yield loss can be accounted for by library issues and the interaction between process and design features. Subtle interactions between manufacturing and design features at smaller geometries result in systematic defects caused by misprocessing, equipment-related problems or printability problems.²

Random defects often are a result of particle contamination. In a mature manufacturing process (for example, at $130 nm technology nodes), more than 50% of the yield loss is caused by random defects. In this situation, the manufacturing process is well-characterized, and high yield can be obtained by designers who follow the required design rule checks that specify feature size, shape and spacing requirements. Design rules are developed by the manufacturer so that, with known process variations, the final product will operate as expected.

But at technology nodes of 65 nm and smaller, predicting yield is more of a challenge. Manufacturing processes are still being characterized, and the interactions between the physical processes and design features can be extremely subtle and not easy to identify. Foundries deliver design rules that are restrictive, but at smaller nodes, process variations are still causing parts to fail. To address these subtleties, foundries also provide recommended design for manufacturing (DFM) rules. These rules are more restrictive than the standard design rules, and sometimes they cannot be implemented because of the required trade-off between meeting the rules (which can take more space in the layout) and meeting design functionality requirements.

Electronic design automation (EDA) tools are available to IC designers to help optimize their layout for manufacturing, that is, to close the DFM gap (Fig. 1). Place-and-route software accounts for process variability and DFM issues. Critical area analysis software identifies areas that have too many connections at a minimum spacing and automatically spreads the traces apart where space is available. Lithography software verifies and modifies the artwork for masks, and software that simulates chemical mechanical polishing (CMP) processes is available to identify areas of the design that may have problems caused by CMP. All of these tools can be used to help improve the initial yield of a design.

1. The yield ramp challenge is reaching a new level for ICs designed and manufactured below 130 nm.

Initial and mature yields

The traditional approach in finding the root cause of defects is the yield management system (YMS). The YMS captures data from the manufacturing process, including optical inspection, machine maintenance histories, parametric test results and, when available, manufacturing test pass/fail test results.

Engineers then study the manufacturing process data and wafer maps and compare the bad wafers to good wafers. Based on this information, they separate failing die into groups based on possible cause of failure. Out of each of these groups, many die are selected to send to the failure analysis (FA) lab to determine the root cause of the failures.

At the FA lab, electrical and physical fault isolation is conducted to localize the defects based on often very vaguedirection from engineering. Some analysis techniques may destroy the part, which means that if the initial presumption was incorrect, FA has to start over on a different part. This investigation process may take days, weeks or even months before the cause of the yield-limiting defectis identified and corrective action can be implemented. The corrective action could be an adjustment to the manufacturing process or a design change.

To speed up yield learning in a changing design and manufacturing environment, a new approach is needed that can quickly identify the root cause of the yield loss. The diagnosis-based yield-analysis or yield-learning flow described here is different than what’s been done before because it involves adding scan-test results diagnosis to the initial investigation of yield loss, rather than just using pass/fail data. Also, the new approach does not rely solely on manufacturing process data, which may not be as useful as it used to be at higher process nodes or readily available to a fabless design company.

As the manufacturing test equipment or tester identifies failed devices, it also can report specifically which pins and cycles the test pattern failed. An automated diagnosis tool can use this test failure data, the test pattern set, and the design netlist to identify the probable cause of the failure quickly. When using both the logic and layout-level representations of the design, the diagnosis tool can produce a precise description of both the defect mechanism and its physical location.

An automated diagnosis system needs to be able to identify all the expected and common defect mechanisms such as small delay, cell internal, chain, bridges and opens. For instance, if the yield-limiting defect is diagnosed to be an “open,” the tool should be able to call out not just the net involved, but the specific net segment down to the metal layers and vias involved. Such detailed information would be vital to the yield-learning process and accelerate failure analysis.

If you’re using an automated diagnosis tool that can handle volumes of data, all the tester failures can be logged and diagnosed. Even in early production runs, this would create a database of thousands of diagnosis results. Then once all this data is gathered, it could be statistically analyzed — greatly decreasing the time it takes to ramp up yield.

Once there’s a volume diagnosis process in place, we need a tool that can perform statistical analysis on volumes of diagnosis results, automatically construct stacked wafer maps, and then drill down into failures that can be put into different categories and analyzed further. For instance, all failures diagnosed to be bridge defects could be divided into different types of bridge defects based on metal layers (Fig. 2).

2. A new diagnosis-based yield-learning approach is needed to address yield-limiting issues that occur when manufacturing advanced-technology and complex IC designs.

For complex interactions at small geometry nodes, systematic effects often appear random on a traditional wafer plot, so we need sophisticated statistical analysis to be able to recognize these hidden systematic yield limiters (Fig. 3).

3. Systematic and feature-related issues for advanced designs are causing an increase in “hidden yield limiters.”

Once the hidden patterns have been recognized, it’s easier to drill down to a single location explaining the failure behavior of the die. Because statistical analysis can generate very specific cause and location data, only a few of the most likely suspects have to be sent to the FA lab. The FA lab can then conduct root-cause verification on a small sample that represents a large population of failing die.

And if the FA lab needs to generate additional tests to verify failures, incremental test patterns can be generated that target specific fault locations. By performing this targeted test, when the die is cut for visual inspection, the chances are much higher that the cut will occur where the fault is, saving on the time and cost of identifying the root cause of the failure.

When designing and manufacturing ICs at 65 nm and below, the interaction of process variation and design features create systematic defects that result in yield problems. Traditional yield-management approaches are proving to be less effective for identifying these problems because of time and equipment limitations and limited access to, or usefulness of, manufacturing process data. At today’s technology nodes, the traditional failure dataset simply is unable to identify all the yield limiters.

Under increasingly competitive market pressures, IC companies need a new process and new tools to better manage yield ramp and boost their mature yields. Not only is analyzing diagnosis results in volume called for, but we also need detailed diagnosis of scan-feature failures that is layout-aware. The evolution of this process is a statistical analysis tool that visualizes, drills down and identifies observable and hidden yield-limiting defects with greater accuracy and more quickly than has ever been done before.