Improving Interconnect Reliability via Optimized Barrier/Seed

Copper metallization, widely used in logic and now commodity memory devices, has led to interconnect geometries that are rapidly approaching nanoscale dimensions. The size of the “killer void” that causes interconnect failure decreases as the interconnect dimension shrinks, while the smaller dimension leads to an acceleration in the growth rate of the void. This has led to a heightened concern for electromigration (EM) failure.

Numerous approaches are taken to improve EM life-time,^1-4 including our use of a PECVD self-aligned barrier (PSAB).⁵ Through the engineering of the dielectric barrier/Cu interface, significant enhancement can be achieved in the electromigration time to failure without compromising the dielectric reliability and resistance to stress migration. The metal microstructure and the interface along the liner and cap layer are both critical to interconnect reliability.⁶ Further improvement is possible by optimizing the metal barrier and seed.

Vias with high-aspect-ratio or “reentrant” profiles may lead to poor metal barrier coverage and premature failure of the interconnect.⁶ A barrier-first approach with resputter (Fig. 1) was developed to provide good step coverage for the via bottom corner and the reentrant area of the feature.⁷ TaN deposition prior to sputter etch eliminates copper buildup under the barrier along the via sidewall. The resputter process redistributes the barrier metal from the via bottom to the sidewall, thus improving sidewall coverage and enhancing reliability.

1. The TaN deposition prior to sputter etch eliminates copper buildup under the barrier along the via sidewall. The resputter process redistributes the barrier metal from the via bottom to the sidewall.

Additionally, with thinner barriers, the film morphology and density become increasingly important to maintaining barrier properties and ensuring a good interface with the copper seed. Furthermore, conformal copper seed step coverage is essential to provide homogeneous metallization for the small features. Novellus Systems' IONX Ta(N) sputtering source uses a high-density plasma and specific ion energy on the Inova platform to optimize the metal barrier microstructure and deliver a film with smooth morphology (Fig. 2). Dielectric reliability also improved with the high-density Ta(N) metal barrier.⁸ RF copper deposition with resputter technology developed on the company's Hollow Cathode Magnetron (HCM) source produces near conformal copper step coverage. A combination of the IONX Ta(N) and RF copper source leads to significant improvements in gap fill capability and EM performance. Significant improvement in both time-to-failure and sigma of distribution (Fig. 3) are possible with the high-density barrier and RF copper seed process.

2. The Hollow Cathode Magnetron (HCM) IONX metal barrier process provides smoother morphology and improved step coverage over traditional PVD.

3. Statistically significant improvements in the downstream (left) and upstream (right) electromigration time-to-failure distributions were observed with the Ta(N) barrier and resputtered seed process relative to the conventional HCM PVD control.

Novel alloy seed

Metal alloying has been widely used in semiconductor processes since the aluminum interconnect era. For copper, multiple alloying elements and approaches have been investigated to improve reliability. A Cu-Al alloy has recently received much attention. Alloying with aluminum increases the incubation time for void growth in copper and decreases the copper drift velocity.⁹ Sputtering has been the preferred deposition approach for copper alloys due to the readily available targets, lower cost and easier process control. T. Vanypre et al. reported improvement in wetting and adhesion with the use of a Cu-Al alloy seed with tantalum barrier.¹⁰ In our dewetting study, Cu-Al alloy seed was also observed to improve wetting on PVD TaN. Better wetting between Cu-Al/TaN may improve gap fill capability and reliability by preventing agglomeration of thin seed layers. An additional benefit of the Cu-Al seed is an improvement in post-CMP defectivity, as lower defectivity was observed even when the ECP-to-CMP queue time exceeded the optimum time window.¹¹ The alloying of copper with aluminum, however, increases the copper interconnect resistance and thus degrades RC delay.

Our investigation of Cu-Al alloy seed integration focused on the trade-off between increased resistance and improved reliability, with the goal of minimizing the RC delay degradation while maintaining the reliability benefits. Through this process development and integration optimization, we developed a novel alloy seed process based on Inova HCM technology.

We used the Cu-Al HCM targets with various aluminum doping concentrations and conducted process integration testing of the PVD process using 65 nm node features and a dual-damascene scheme with Coral as the bulk low-k dielectric. Two metal layer damascene structures were used for reliability investigations. Figure 4 shows the normalized RC delay as a function of aluminum concentration for both conventional and novel alloy seed processes. We observe a linear correlation between aluminum doping and RC delay (due to line resistance shift). Precise control over RC delay shift can be achieved by modulating the aluminum dopant concentration. This precise control allows the end users to tailor the alloy seed concentration to meet their specific product requirements.

4. Both conventional seed and novel alloy seed directly increase RC delay.

Linewidth dependence of copper resistance has been a concern for copper alloy seed processes. Previous published results suggest a clear linewidth dependence of copper resistivity when alloy seed thickness is modulated to control the aluminum doping concentration.⁹ This dependence was attributed to the thicker alloy seed in the trench decreasing the median grain size, especially in wider geometries. In this work, where the alloy seed thickness is held constant for all process conditions, line resistance was invariant with linewidth at low aluminum concentrations (Fig. 5). For the high aluminum doping process, however, a higher resistance shift is observed with smaller trench widths. The higher resistance shift for narrow trench may be attributed to limited grain growth as a result of high aluminum concentration within the trench.

5. Resistance rises with greater levels of aluminum doping, but can increase as lines narrow. Resistance shift is normalized to pure copper at 1.0.

Downstream package EM test results suggest a clear correlation between time to failure (TTF) and the aluminum doping concentration (Fig. 6). Significant EM improvement can be achieved with the Cu-Al alloy approach, but leads to a large increase in RC delay. A measure of the trade-off between EM improvement and increase in RC, defined as the EM improvement efficiency, was recently proposed by S. Yokogawa et al.¹² Here it was concluded that with Cu-Al alloy seed, although significantly improving EM, the EM improvement efficiency was not as high as the CoWP metal cap approach. There have been many studies of reliability improvement with cobalt-based cap processes, and although such a process enables large improvement in EM lifetime, it remains difficult to implement because of degradation in dielectric reliability, process control challenges and higher cost.^4,13

6. Downstream EM performance as a function of aluminum doping concentration for samples with conventional alloy seed. The TTF improves from no doping to low, medium and high doping.

We developed a novel alloy seed approach with the HCM PVD process to enhance the EM improvement efficiency without compromising dielectric reliability and stress migration performance. Figure 4 shows a comparison of RC delay using the conventional and the new alloy seed approach. The EM improves with alloy seed as plotted against normalized line resistance (Fig. 7). We collected the downstream package EM data over a wide range of line resistance shifts for both conventional and novel alloy seeds. Consistently higher EM improvement efficiency, defined as the slope of the plot in Figure 7, is demonstrated with the novel alloy seed process.

7. Comparison of the downstream EM improvement efficiency between conventional alloy seed and novel alloy seed processes developed on an HCM PVD chamber.

The improvement in EM with a Cu-Al alloy is attributed to a slower copper drift velocity and lower void growth rate.⁹ Aluminum accumulation at the dielectric barrier (SiCN) and copper interface was also detected.⁹ We conducted SIMS depth profiling to understand the aluminum distribution within the Cu-Al alloy seed (Fig. 8). Increased thermal budget after CMP leads to aluminum diffusion through copper and accumulation at the SiCN/Cu interface. Based on the Al-Cu phase diagram, aluminum is completely soluble in copper at <1% (at). Thus, concentration gradient driven diffusion alone does not lead to solute accumulation at the SiCN/Cu interface. The copper surface is covered with CuO_x prior to SiC deposition. Plasma treatment is used to reduce the surface CuO_x prior to SiCN deposition. Even though much development was done to minimize the oxygen content at the SiCN/Cu interface, any residual oxygen at the SiCN/Cu interface may be detrimental to reliability.¹⁴

8. SIMS of aluminum in (from top) SiCN/CMPed ECD Cu/Alloy Seed/Ta film stack. Post-CMP, post-SiCN deposition, post-anneal at 30 min/400°C, post-anneal at 30 min/400°C + 360 min/350°C.

The aluminum is known to segregate to the Cu-Al film surface, transforming to Al₂O₃ with a subsequent anneal.¹⁵ It is plausible that the residual oxygen at the SiCN/Cu interface can react with aluminum and drive the aluminum to segregate at the SiCN/Cu interface. The aluminum segregated at the SiCN/Cu interface can react with oxygen, leading to a better SiCN/Cu interface and improved electromigration. This mechanism is also consistent with our previous study of Ti(N) barrier integration.¹⁶ The SiCN/Cu interface was improved with the use of Ti(N) metal barrier, where titanium diffuses through the copper and accumulates at the SiCN/Cu interface.¹⁶ The improvement in the SiCN/Cu interface, along with slower copper drift and reduced copper void growth rate, greatly enhances EM performance with use of Cu-Al seed. Although the mechanisms are still under investigation, we believe that the novel alloy seed process allows the formation of a homogeneous copper microstructure inside small features and strengthens the Cu/SiCN interface, leading to improved EM resistance.

We also studied the dielectric reliability of structures with the novel vs. conventional alloy seed. Figure 9 shows Weibull plots of line-to-line breakdown voltage for samples with different alloy seed processes. No significant difference is seen in the α values of the different distributions. The samples with the novel alloy seed process show higher β, which can be attributed to CMP and line-space uniformity improvement, thus considered insignificant. Overall, both novel alloy seed and conventional alloy seed demonstrate equivalent dielectric reliability compared with the pure copper seed reference process.

9. Summary of the line-to-line breakdown voltage data for pure copper seed, conventional alloy seed (low aluminum doping), medium aluminum doping, and novel alloy seed (low aluminum doping), medium aluminum doping.

In terms of stress migration (SM) performance, the novelalloy seed processes with all tested doping concentration levels demonstrated excellent performance, matching that of the reference pure copper baseline process. Conventional alloy seed also shows excellent SM performance except at the low aluminum doping concentration. The root cause of this discrepancy requires further investigation.

Various approaches have been developed to meet the ever-increasing requirement of electromigration resistance. A PECVD self-aligned barrier (PSAB) process based on Vector architecture can enhance the SiCN/Cu interface with the formation of a shunt layer near the SiCN/Cu interface, prolonging the growth of nascent defects (voids) within the interconnect structure.⁵ As previously discussed, an alloy seed approach improves the EM performance through different mechanisms. The capability to combine various low-cost, low-risk reliability improvement approaches to meet the increasing reliability challenges will provide larger benefits than employing radical process changes.

Figure 10 illustrates our preliminary result in exploring the synergy effect in combining PSAB and alloy seed processes. Figure 10 shows that PSAB process or Cu-Al alloy seed alone may provide EM improvement. Combining PSAB and Cu-Al seed leads to further gain in EM time-to-failure. This synergy effect is not limited to PSAB alloy seed, but is applicable to other approaches. Recent studies suggest a similar synergy between self-aligned barrier and MnO barrier.¹⁷

10. Progressive improvement in EM is demonstrated with Ge-PSAB, alloy seed, and Ge-PSAB + alloy seed demonstrating process synergy. SiCN with pure copper seed is the reference.

Conclusion

Optimization of the metal barrier and copper seed processes provides reliability improvement through a high-quality metal barrier and homogeneous copper metallization. Further EM enhancement can be achieved through a copper alloy seed approach. A novel alloy seed process based on HCM Cu-Al technology provides higher EM efficiency and does not compromise the dielectric reliability and stress migration performance. This novel alloy seed technology offers a low-cost solution for improving the reliability of copper interconnects. Furthermore, synergy between the Cu-Al alloy seed and PSAB demonstrates the capability to combine these different approaches to maximize the electromigration benefit.