Micro Copper Contacts Replace BGA, Improve Reliability

Portable electronic devices have stringent mechanical shock requirements because of their form factor and typical usage conditions. Various methods are used to allow semiconductor packages assembled with lead-free solder alloys to meet device lifecycle needs in these applications. Board-level underfilling of package components is one approach, but this method increases assembly cycle time and cost. And a potential negative effect of underfill is reduced thermal cycling performance caused by fatigue. Adjusting the alloy composition is another method used to improve mechanical shock performance, but this solution may also contribute to diminished thermal cycling performance.

1. Cross-section of the µPILR interconnection soldered onto a PCB.

In the first part of our analysis, an industry-standard stacked-die chip-scale package (CSP) was used as a control and compared to an identically constructed package thatreplaced the BGA interconnections with an array of solid copper contacts. The stacked-die CSP product configuration is commonly used in the memory subsystems of mobile electronic devices, such as cellular handsets, which typically contain a heterogeneous combination of non-volatile memory (NVM) and RAM. The characteristic life and failure mechanisms of each type of interconnection were examined, with conclusions made regarding the performance of the µPILR interconnection. The work was then expanded to investigate the reliability of a package constructed using the µPILR interconnect in a package-on-package (PoP) configuration.

To address future increases in system functionality requirements, PoP designs will need to accommodate increasing I/O counts for the top and bottom packages in the stack, while maintaining or reducing the PoP form factor. This will require finer interconnect pitches and higher routing densities. Finer interconnect pitches require tighter package mechanical specifications to maintain high yields during the assembly of the stacked package to the main PCB. Key factors affecting PoP assembly yields include controlling package warpage, and the solder volume in the interconnect joint to avoid opens or solder bridging during the solder reflow process. Furthermore, the reliability requirements for drop test and thermal cycling must be maintained, ideally without the need for board-level underfill. For the µPILR PoP evaluation, the area-array bottom package of the PoP used an aggressive 0.4 mm pitch while the perimeter-array top package used an equally aggressive 0.5 mm pitch.

An evaluation was conducted to compare the reliability performance of the µPILR interconnect with an industry-standard BGA product using a 0.8 mm pitch area-array stacked-die CSP design, which was provided by a partnering integrated device manufacturer (IDM). The µPILR and BGA packages were essentially equivalent in design and assembly. The key difference in the packages being evaluated was that the lead-free solder ball (98.5% Sn 1.0% Ag 0.5% Cu (SAC 105)) on the BGA package was replaced by an integral solid copper contact on the µPILR package. The package had a body size of 13.0 × 11.0 × 1.04 mm, and there were 108 total package pins that were divided into two nets. One net consisted of the four corner pins, one in each corner, and the other net consisted of the remaining 104 pins in the array. The four corner pins used were dummy pins and non-critical to device function (NCTF). This NCTF net was not analyzed for comparison purposes. The remaining 104 pins were critical to device function (CTF) and monitored as a continuous package daisy chain with the test board. The µPILR and BGA packages used two layer bismaleimide triazine substrates and matched assembly material sets. Mechanical replication of a functional die-stack assembly was achieved using four mechanical silicon die of 100 µm thickness. A compliant die attach material and filled epoxy overmold was used.

Test boards for drop testing and thermal cycling were designed to the specifications outlined in JEDEC standard JESD22-B111. 350-µm-diameter via-off-pad (VOP), non-soldermask-defined (NSMD) pads were used on the test boards. Both the µPILR and BGA test samples were SMT soldered to the test board using a lead-free 96.5% Sn 3.0% Ag 0.5% Cu (SAC 305) no-clean solder paste. The SMT solder paste was applied using 5.0-mil-thick stencils with 16.0 mil and 13.0 mil square apertures for the µPILR and BGA components, respectively. The difference in stencil apertures was required to control the total solder volume for each interconnection type.

Drop testing to calculate characteristic lifetime under mechanical shock conditions was conducted to the specifications detailed in JEDEC standard JESD22-B111. Drop test components were subjected to a peak load of 1500 g ±100 g, with a peak pulse duration of 0.5 msec. The test boards were assembled with all 15 test sites fully populated. Figure 2 shows the Weibull plot for the µPILR and BGA drop testing. These results were calculated to be statistically different using 90% confidence bounds. The characteristic failure mode for the BGA control samples was solder joint cracking at the package pad-to-solder interface. There were no solder joint failures in the any of the µPILR components. The eventual failure occurred from traces cracking in the package substrate, where the trace exiting the µPILR contact pad flairs down to the routing width of the trace.

2. Drop testing shows that the B1 life (1% failure rate) calculated for the BGA components was 193 drops, and the characteristic life, η, was 614 drops. At 494 drops, the B1 life of the µPILR components was 2.55× greater than the B1 life of the BGA control. Furthermore, the characteristic life was calculated to be 1145 drops, 1.86× greater than the calculated η value for the BGA control.

Board-level thermal cycling from -40°C to 125°C was conducted to IPC-9701 TC3 specifications using sample sizes of 45 µPILR components and 45 BGA components. Figure 3 shows the Weibull plot for the µPILR and BGA thermal cycle testing. These results were calculated to be statistically different using 90% confidence bounds. Through failure analysis, it was shown that the BGA control failed because of solder cracking at the package substrate pad-to-solder ball interface, while the failure mode for the µPILR packages was cracking of circuit traces in the package substrate, similar to what was seen in drop testing. Additional testing was conducted to further validate the reliability of the µPILR interconnection in alternate applications. One of the alternate applications, PoP, is further discussed below.

3. B1 life was calculated to be 454 cycles for the BGA control and η was calculated to be 855 cycles. The µPILR samples had B1 and η values of 664 and 1524 cycles, respectively, a substantial improvement.

µPILR PoP design, assembly

A µPILR PoP test vehicle was fabricated and subjected to drop testing and thermal cycling. The top package, which is characteristically used for a memory subsystem, had 168 total pins arranged in two rows of 0.5 mm pitch around the package perimeter. The bottom package, which is typically used for a baseband or mobile applications processor, had 672 total pins at 0.4 mm pitch arranged in a depopulated area array. A series of package daisy chain nets were used to track the electrical continuity of the interconnections in both the memory and logic packages during reliability testing. The four interconnections in each corner of the bottom package were monitored on a unique net as NCTF mechanical joints. All other nets of both the top and bottom packages were considered CTF. The µPILR substrates were fabricated using ROHS-compliant glass-reinforced FR4 dielectric materials. The µPILR substrates were assembled into test packages using conventional package assembly processing and materials. The test vehicle used three mechanical silicon die in the top package and one mechanical silicon die in the bottom package. A compliant die attach material and filled epoxy overmold was used in both the top and bottom packages.

The SMT assembly of our µPILR PoP test vehicle was performed by a Tier 1 electronic manufacturing services (EMS) provider. The components were mounted and stacked to the reliability test board using high-volume SMT equipment. The SMT process was performed in the following sequence:

• solder paste was applied to the reliability test board using a stencil
• the logic package was placed over the solder paste on the test board with a high-volume pick-and-place machine
• the memory package was dipped into a paste containing both flux and solder particles
• the memory package was placed directly on the logic package
• the PoP stack was put through a solder reflow process

No secondary package underfill was used subsequent to the SMT process. All solder used in the study was SAC 305. The substrate pad and µPILR interconnect finishes were electroplated NiAu. The VOP test board pads were 250-µm-diameter, NSMD with a copper organic solderability preservative finish. Figure 4 shows an SEM cross-section of the completed µPILR PoP test vehicle after the SMT assembly process. The top package solder joints at 0.5 mm pitch are approximately column-shaped, which can help to reduce the risk of solder bridging, especially at finer interconnect pitches. The bottom package solder joints at 0.4 mm pitch have a very low profile, <150 µm. In assembly trials of 0.4 mm pitch area-array devices, we have found that the presence of the µPILR copper pins can help improve SMT yields of the package-to-board interface by reducing the incidence of solder bridging vs. a more conventional BGA package with standard solder pads. It is suspected that a SMT yield benefit arises from the enhanced solder wetting of the copper pin combined with the mechanical stand-off that keeps the logic package away from the test board during the refold profile.

4. The µPILR copper pins can clearly be seen within the solder joints.

µPILR PoP reliability testing, results

Following the SMT process, the µPILR PoP was tested according to JEDEC drop test standard JESD22-B111, as well as thermal cycling from -40°C to 125°C per IPC-9701 TC3 specifications. Figure 5 shows a Weibull plot of drop test results for the critical package nets. The failure mode for the µPILR PoP test vehicle was solder cracking in the bottom package interconnection with the test board, along the test board pad. For thermal cycling from -40°C to 125°C, there were no failures observed for the µPILR PoP up to 2500 cycles.

5. The B1 life was 73 drops and the characteristic life was 457 drops. This reliability level is more than twice the target of 30 drops per the JESD22-B111 standard, and is accomplished without the need for secondary package underfill.

Conclusions

The results of the µPILR interconnect and BGA comparison testing demonstrate that an alternative interconnect approach, such as the µPILR copper contacts, may achieve an increase in characteristic life over conventional lead-free BGA interconnections in both drop testing and thermal cycle testing. It is significant to note that the results were achieved with a nickel-gold finish on the substrate pads and SAC 305 solder.

Even better drop test results may be achieved by using alternate µPILR contact finishes and solder alloys, e.g., copper with OSP and lower silver content alloy. For this reason, the µPILR PoP offers a wider process window in terms of interconnect materials, which can result in greater flexibility within the SMT supply chain and assembly process.

The high reliability of the µPILR PoP is a result of the copper contact, which acts as a crack “stop” that arrests the propagation of any stress-induced solder joint cracks at the substrate pad. This feature is absent in conventional BGA interconnections, and it has been previously demonstrated that solder failures at the substrate pad interface in BGA packages are caused by fatigue accumulation under high tensile stress or high plastic strain in drop test and thermal cycle, respectively. In the comparison test, the characteristic failure mode of the µPILR interconnections showed a statistically significant increase in drop test reliability over the BGA control.

The authors would like to thank Dr. Ilyas Mohammed, Celia Lopez, John Tseng, K.M. Bang, Ellis Chau, Wei-shun Wang, Dr. David Baker, Long Huynh, Daniel Buckminster and Hala Shaba.