Crossing the Semi/Nanotech Bridge

The application of nanotechnology to materials such as shielding, strengthening structures, enhancing thermal and electrical conductivity has reached the point at which some preliminary applications are already in the market. Increasingly, we will see more coming online over the next two to three years. Nanotech is widely interrelated, and many semiconductor companies — Intel and Samsung being examples — are seriously looking beyond their usual areas of expertise to bio and medical applications.

Ahmed Busnaina, professor and director of Northeastern University's NSF Nanoscale Science and Engineering Center for High-Rate Nanomanufacturing (Boston, Mass.), said, “There are many nanoparticle and some carbon nanotube [CNT] applications being developed to combat cancer. These development areas should progress faster than most of the others.”

Another large development effort focuses on energy applications — mostly photovoltaics and batteries. Nanotech for photovoltaic uses is being seriously considered, particularly for cells made out of polymers.

At Northeastern University and other major research centers, work proceeds on new architectures such as nanotube-based FETs or mechanical CNT devices such as a transistorless switch for nonvolatile memory. “The semiconductor industry is finally looking into this,” Busnaina said. “In fact, CNT NEMS nonvolatile memory devices did not make it into the ITRS roadmap until this year. Just two or three years ago, the industry did not expect to use this.” Other work uses CNTs for device interconnection.

From a semiconductor industry perspective, nanotech isnot progressing as fast as in some other fields because the industry reluctantly adopts new manufacturing technologies. Central to adoption is designing nanomanufacturing processes compatible with mainstream semiconductor manufacturing processes. This means making the new process similar to a traditional one such as CVD or electroplating, for example. If this is done (and metals such as gold or iron are avoided), nanotech adoption is simplified.

The industry is becoming more accepting, which shows in the development of CNT applications for transistors, nonvolatile memory and networking circuits. Some companies are using nanotubes for power and shielding in cellphone or satellite applications. Certainly, their lightness makes them attractive for military applications — possibly more effective than metals.

Today's biggest problem is assembly. “While it's being done with CNTs, what is done is taking one or two of them, putting it between two electrodes, and depositing some material. Everybody cheers, 'Hey, we have an oscillator, a transistor, or a device!'” Busnaina said. “The real trick is to do it across a whole wafer with decent yield. So far, manufacturers have been unable to scale the process and not too many are working on scaling. We have conducted directed assembly on a 100 mm wafer, whether it is assembly of a single nanotube for a mechanical switch, NEMS, or assembly of nanotubes for devices.”

This wafer-level assembly capability enables CNT wire work that can go from the wafer's top to its bottom, with wires 80 nm wide or smaller (Fig. 1). “We've also done single-wall CNT assembly in switches over the whole wafer and sufficiently controlled the process to obtain an 80% assembly yield. We're optimizing our assembly processes for nanoparticles and nanotubes. Scaling to a 150-200 mm wafer will require more work,” Busnaina said.

1. Single-wall switch designed and fabricated using directed assembly to make one single-wall carbon nanotube (SWCNT) per switch as the actuation element at wafer level. (Source: Center for High-Rate Nanomanufacturing)

Nanotech metrology

Alain Diebold, Empire Innovation Professor of Nanoscale Science at the University at Albany's (New York) College of Nanoscale Science and Engineering (CNSE), and a leading metrology expert, is on a quest for improved microscopy. “There's a need for simulation and modeling to go along with microscopy, in some cases to serve as a guide for what is required,” he said. “Can one look for some unexpected atom in an atomic column of a single crystal that causes an observed phenomenon? Is it possible to search for an interstitial atom that creates a defect? Should you be seeking certain defects in a material that you've never observed before? And what will you really see when you look for a defect in an electron microscope, and how do you know it's what you're looking for unless you have years of experience like people have in silicon materials?”

Diebold thinks we must prepare for the unexpected, and this requires far more cooperation between simulation, modeling and microscopy, as well as all sectors of metrology. Another area of concern is the difficulty in doing regular and high-frequency electrical test on a number of these new materials. It is a problem, because many materials have an electrical functionality to them — beyond CMOS, nanobio, MEMS and NEMS devices — that is challenging to probe because of nanoscale dimensions. It is also a challenge to understand the correlation between nanoscale and mesoscopic dimensions among several devices, to ensure that they all work together.

To a point, when anything is modeled there is a slight tendency to drift away from reality. It must be considered, however, that there are different kinds of modeling. There is the very fundamental kind, where a part is most easily tied into the experiment. For instance, what does it mean to have a band structure in a nanoscale dimension, where this can be tied to an optical measurement or another kind of measurement?

There are different levels of nanoscale modeling. For example, can one model a fluid flow through a NEMS' very small channels, or is some kind of empirical model better, as has been the case with transistors, for example? There are empirical models of how current flows — and transport models seem to have some link to fundamental properties; however, by the very nature of the modeling, they seem to be one or two steps removed from a fundamental simulation. So, whether it is graphene or organic electronic materials, a link is needed between fundamental reality and something that can be used in a device simulator.

“Often the available modeling decides the work's direction,” Diebold said. “For example, to a great extent the effort to figure out how to use CNTs as a channel in a transistor stems from the fact that people understand how to model transistors, and they understand carrier transport in CMOS transistors. This enables them to perform preliminary carrier transport measurements for a CNT-based transistor and then build new models based on improved understanding of the new physics observed for CNTs. So they're taking these steps by staying in familiar territory and taking a small, incremental peek beyond.”

Associate Professor of Nanoscience Vincent LaBella, CNSE's “spin doctor,” concentrates on spintronics, in which the electron's spin is used in semiconductor devices. Right now, the research is concentrated on logic, to produce higher-speed devices that consume less power. The work has been boosted by recent developments over the past year that have shown that silicon is one of the better semiconductors for spintronics, primarily because the spin lifetime is very long — 10-100× longer than in III-V materials.

Because all the industry and machinery available is designed to process silicon, it makes it easier to work with spintronics. “We've tried to do both spin injection and spin readout using nanoscale contacts to silicon,” LaBella said. “This is a relatively simple structure and it involves stacks sufficiently outside of the conventional CMOS nanotechnology realm, which makes it challenging. It involves very thin layers — 1-2 nm — of ferromagnetic metals and different oxides, patterned within a few microns of each other on a silicon chip. This requires some thin-film deposition and nanoscale lithography.”

For these devices, the hurdles lie in processing. CMOS fabs dislike materials like iron and Permalloy, magnesium oxide and so forth; these are outside the general scope of what a standard facility can do. This requires finding tools and equipment that will not come into contact with the CMOS area.

Presently, using silicon, it is possible to electrically inject spin-polarized current, and read it out electrically. “This means you can have contacts that read out a current which is proportional to the spin polarization,” LaBella said. “In III-V materials, it is much more difficult to do this electrical readout, and optical means are used. This works well for III-V materials because they are optical materials, but not for silicon. So this electrical readout has been a big breakthrough for silicon and has opened the door for us to think about using this now in device architecture. Meanwhile, we have lithography resources that enable us to make all these things in silicon.”

LaBella is trying to use spin to send signals in silicon for interconnects. If this long-lived spin in silicon could be used to send signals, it might replace copper, leading to truly monolithic integration. The researcher is in the process of making the test structures, and thinks that in the coming years he will have a working model to experiment with.

2. Experimental setup for the ballistic spin transport metrology tool that can study effects of the interface on the spin injection efficiency from a ferromagnetic metal into silicon. The directions of the magnetization of the sample and tip are indicated by MSample and MTip, respectively. (Source: CNSE)1

Christopher Borst, assistant vice president for engineering and integration at CNSE, observed that at UAlbany, students, faculty and staff are performing research in nanoscience, nano-engineering, nano-bioscience, and nano-economics; all the necessary toolsets to examine nano-phenomena as they relate to silicon processing.

“EUV lithography has provided the industry with challenges clearly displayed in the SIA roadmap, but the investment is starting to pay off,” Borst said. “We're seeing some of the improvements from our Alpha Demo Tool. Among them are demonstrations of tool and technology capabilities for driving down to dimensions beyond current immersion resolution capability [Fig. 3], and equipment advances such as source and reticle stage upgrades that should enable much better throughput than before. Although wholesale implementation of EUV toolsets in mainstream fab facilities is still years away, and there are still significant hurdles, we clearly see progression — progression in defectivity, progression in process results, and also progression in throughput, the latter being the item that has significant attention of our industry consortium partners.”

3. Shown here are 35 nm half-pitch lines/spaces, and 36 nm dense contact holes, patterned using EUV lithography. (Source: CNSE)

Continued device scaling will push us into alternate geometries, whatever term is used — finFET, trigate. Work is proceeding to determine what alternate gate materials to use. In terms of high-k and metal gate, alternative designs such as finFET are essential. In interconnects, air-gap insulation is eventually a direction that must be taken. Some good work has been done recently considering an air gap strategy that induces the air gaps only in the critical paths, the slowest areas of the interconnect.

Funding is an endemic problem for nanotech R&D. There are consortia, but their contributions translate into just a few million dollars — not exactly a fortune considering the task — and prospective R&D teams must often jump through many hoops to get the money. For example, in some cases, they cannot propose anything without first selecting a possible partner company, discussing it with the company first, and then submitting the proposal. This is limiting because some research is long-term and companies want short-term return on investment. Companies with their own research centers or that participate in others tend to assign the same people already performing classical device work to nanotech research. Researchers often tackle matters that are very difficult and whose application may be unclear; companies tend to shy away from this in fear of investor rage. Achieving widespread, real and practical nanotechnology applications will likely require increased funding of even long-term research.