How Might 3-D ICs Come Together?

Whether we are looking at the device level, where gate and interconnect delays must be considered, or at the system level with bandwidth and latency issues, a perfect storm is brewing, which requires changes in how the industry fabricates microelectronic functions. Key factors influencing this change include delays in the International Technology Roadmap for Semiconductors (ITRS)¹ and reports of problems with continued scaling of copper and low-k wires due to difficulties in integrated porous low-k dielectrics.² At the same time, up to 50% of supplied power is already being dissipated in chip interconnects, and line resistivity and capacitance have become problems even for copper interconnect lines at 65 nm.³

These problems were first clearly identified in 2001 when IEEE fellows Saraswat, Reif and Meindl predicted that “chip interconnect threatens to…decelerate or halt the historical progression of the semiconductor industry…” and proposed that 3-D integration of circuits should be rigorously explored.⁴

The need became more visible in September 2007 when the Semiconductor Industry Association (SIA) announced, “Our ability to shrink the size of the transistor will be limited by physics sometime within the next 10-15 years.” Entirely new device structures such as carbon nanotubes, spintronics or molecular switches are not likely to be ready for >10-15 years.⁵ Again, new assembly methods such as 3-D IC integration were proposed.

Memory latency adds still another motivation for 3-D integration, with memory access known to be increasing at a much slower rate relative to processor speeds, thus causing the processor to stall while waiting on memory to access data. In multi-core processors, the problem is exacerbated and may require the direct bonding of memory to processors.⁶

In February 2005 when “ICs Going Vertical” was published,⁷ few readers were aware of the technical advances occurring in 3-D IC integration, and considered 3-D technology as stacking and wire bonding — a back-end packaging technology.

Today, 3-D integration is defined as a system-level integration architecture wherein multiple strata (layers) of planar devices can be stacked and interconnected using through-silicon vias (TSVs) in the Z direction (Fig. 1).

1. A 3-D wafer-level stacking scheme using a through- silicon via approach. (Source: University of Alberta)

A number of process sequences have been developed to fabricate such stacks, all of which depend on the following enabling technologies:

• TSV formation: The Z-axis interconnects are electrically isolated connections through the substrate (silicon or other semiconductor material), where the diameter of the TSV is dependent on the degree of access needed at an individual strata.
• Thinning of the strata to ~75-50 µm for initial applications and ~25-1 µm in the future.
• Alignment and bonding either die to wafer (D2W) or wafer to wafer (W2W).

By inserting TSV, thinning and bonding, 3-D IC integration eliminates a significant portion of the packaging and interconnect processes. However, it is not totally clear where these processes will be performed in the overall manufacturing sequence. It is likely that TSV processing will be performed by IDMs or foundries during IC fabrication and thinning, and bonding will be performed by IDMs or outsourced semiconductor assembly and test suppliers (OSATS) during the packaging operation, but that may change as the technology matures.

It is quite possible that, in the future, this 3-D IC technology adoption period will be looked upon as the period where the lines between IC fabrication and IC packaging began to blur.⁸

TSVs can be formed during the IC fabrication process (vias first) and those fabricated after (vias last). In the former case, front-end-of-line (FEOL) TSVs are fabricated before the IC wiring processes occur on chip, and back-end-of-line (BEOL) TSVs are fabricated at the IC foundry during the metal wiring processes.

FEOL vias are fabricated in the blank silicon wafer prior to any CMOS processing (Fig. 2). The conductive material must be resistant to subsequent thermal processes (usually 1000°C+), thus the selection is limited to polysilicon. TSVs fabricated in the BEOL can consist of either tungsten or copper and, in general, formation occurs early in the process to ensure the TSV will not occupy valuable interconnect routing real estate. In both the FEOL and BEOL cases, the TSV must be designed into the IC wiring.

2. The process sequence is depicted for FEOL polysilicon TSV (a) and BEOL tungsten or copper TSV (b).

TSVs can also be fabricated after the CMOS device is completed. This can be done either before or after the bonding process. Since the CMOS device is complete, the wafer will no longer be exposed to high temperature cycles after via formation, thus allowing the use of copper conductors. Obviously, open areas to fabricate these vias must have been designed into the die.

If given a choice, TSV formation in the foundry, FEOL or BEOL, is the simpler process. BEOL interconnect layers are complex composites of different dielectric and metal layers. Etching through such layers is difficult and product-specific. Creating TSVs after complete IC fabrication by etching through the BEOL layers will block routing channels, increase routing complexity and increase chip size, possibly requiring an additional routing layer.⁹ Now that foundries like TSMC (Taipei, Taiwan) and Chartered (Singapore) are beginning to announce their intention to move to volume TSV production, having vias fabricated during the IC fabrication process will become a more viable option.¹⁰

Most 3-D IC processes are aiming for individual IC tiers considerably thinner than 75 µm. There are two options for handling such thinned device wafers (Fig. 3). In process A, wafer 2 is bonded directly to the IC stack in a face-down configuration. The wafer is then thinned to the desired thickness, which may expose the backside of the TSV. Backside processing subsequently etches the vias (if not already there from the foundry) and backside I/O pads are formed. Such stack thinning can also be done if known good die (KGD) rather than full wafers are bonded face down to the stack.

3. Thinning on a 3-D stack (A) is compared to mounting the device wafer onto a carrier wafer for thinning and backside processing (B).

In process B, wafers are mounted on a temporary carrier wafer, usually a silicon or glass wafer for thinning and backside processing. The IC wafer is mounted face down onto the carrier wafer and thus must be subsequently bonded in a face-up configuration onto the 3-D IC stack. Since the wafer is temporarily bonded with adhesive onto a carrier, further process steps have to be limited to temperatures at which the adhesive is stable.

After thinning and final backside processing, the device wafer can be aligned to the stack, bonded and the carrier removed (wafer-to-wafer bonding), or the device wafer is released from the carrier wafer onto dicing tape on a dicing frame for subsequent transfer as KGD.

W2W stacking is most practical for high-yielding individual wafer layers, like memory, which all contain the same size die. D2W bonding is best suited for lower-yielding wafer layers and/or die that differ in size. Assembly time is an issue for D2W bonding since this offers no wafer scale economics.

There are two main technologies for “drilling” TSVs: dry etching or Bosch etching, and laser drilling (Table 1). Developed more than a decade ago for the MEMS industry, the Bosch process alternates between short isotropic SF6 plasma etches for the removal of silicon and short C₄F₈ plasma deposition steps for sidewall passivation. As can be seen in Figure 4, etch rate has increased steadily over the past few years.

4. Etch rates more than double over a span of three years. (Source: Tegal)

In laser technology, significant advances have led to its use in memory stacking efforts at Samsung (Seoul, Korea). Most of this new data has come from Alexey Rodin and co-workers at XSil (Dublin, Ireland). Being a maskless process, laser processing eliminates the photoresist coat, lithography expose, develop and strip processes. However, there are still questions as to whether the laser vias can be scaled down as TSVs shrink below 10 µm in the future.¹¹

Oxide (SiO₂) insulation layers are typically deposited by CVD using silane (SiH₄) or TEOS. If the TSVs are being insulated and filled after chip fabrication, care has to be taken with the deposition temperature. Typical TEOS deposition processes are in the 275-350°C range to achieve a functional insulator of the appropriate density.

Several applications such as CMOS image sensors and memory are requesting lower deposition temperatures.¹² Such lower-temperature oxide deposition techniques are being developed by Alcatel (recently acquired by Tegal, Petaluma, Calif.), and other toolmakers.¹³ IMEC (Leuven, Belgium) has reported on the use of Parylene precursor, which can be deposited at room temperature, as a conformal organic insulator for TSVs.¹⁴

Performance of the barrier, seed and plating technologies depends on the via diameter and aspect ratio (AR). It is important to know what aspect ratios will be required for various via diameters both in terms of creating the blind vias and filling them. Most cost of ownership (CoO) models show that via formation and via filling are the major cost barriers for 3-D, but this clearly depends on size, pitch and aspect ratio. Although tool vendors and materials suppliers are working hard on aspect ratios of 10:1 to 20:1, it is not clear in the short term which application these ARs are designed to address.

Amkor (Chandler, Ariz.) has shown that lower CoO will be obtained by using thinner layers in conjunction with smaller vias, since such vias with lower ARs will always be less costly to fabricate (Fig. 5).¹⁰

5. As grinding thicknesses decrease, via manufacturing costs decline. (Source: Amkor)

It is likely that as 3-D technology evolves and applications require via and pitch shrinkage, there will also be a decrease in layer thickness. Tests thus far reveal no deleterious effects from backside thinning down to sub-5 µm silicon; therefore, it is likely that manufacturability, not electrical performance, will be the limiting factor. In addition, thickness is important when considering vias first or vias last. In the latter, there is an additional 6+ µm of interlayer dielectric oxides to cut through before silicon etching begins. For thin silicon layers, this will have a significant impact on the aspect ratio.

None of the 3-D applications such as CMOS image sensors, memory, memory on logic, etc., show AR>5 being required the next 2-3 generations. It is not until we get to TSV diameters of ~1 µm or less that we can anticipate seeing AR in the 10-20 range.¹⁵

For copper vias, both the TiN adhesion/barrier layer and copper seed are deposited by sputtering. However, to achieve high-aspect- ratio (AR>4:1) step coverage, conventional PVD DC magnetron techniques are inadequate. Ionized metal plasma (IMP) based PVD technology enables more conformal deposition of copper seed layer on the sidewalls and via bottoms. Because of the directionality of the deposited atoms and use of ion bombardment to sputter material from the bottom of the via to the sidewalls, IMP provides superior step coverage and barrier/seed layer conformality.¹⁶

Some of the wafer bonding technologies that have been examined for 3-D integration include:

• Oxide (SiO₂) fusion bonding
• Metal-metal bonding
• Cu-Cu fusion bonding
• Eutectic bonding (Cu/Sn)
• Bumping (Pb/Sn, Au, In)
• Polymer adhesive bonding

Because of the feature sizes, all of the bonding technologies shown in Figure 6 require extremely smooth, flat, clean surfaces. Although all of these technologies appear viable, there has been a tendency to migrate toward the metal-metal bonding technologies because of the simultaneous formation of the mechanical and electrical interfaces.¹⁷

6. Three bonding approaches. (Source: James Lu, RPI)

Copper-copper bonding

Direct copper bonding involves bonding conditions of 350-400°C for >30 min under pressure followed by nitrogen annealing at 350-400°C for 30-60 min. Highly polished copper surfaces and a high degree of cleanliness are required. Commercial tools such as those from EV Group (St. Florian/Inn, Austria) and SUSS MicroTec (Waterbury, Vt.) require multiple bonding heads per alignment tool in order to achieve reasonable throughput. A process such as that reported by Ziptronix (Morrisville, N.C.) called the direct bond interconnect (DBI) process reportedly increases this throughput substantially by capping the TSV with a metal that allows coplanar CMP of oxide and metal and uses the exposed oxide surface, treated by a patented surface treatment to bond the die or wafers in 1-2 min, under ambient conditions in a standard bonder/aligner tool. At 350°C under pressure, a monolithic metallic interface is formed in a lower-CoO bonding operation.^12,17

Table 2 summarizes nine different process flows for 3-D integration — from wafer processing through bonding.

Part 2 of this article will highlight the key players in 3-D commercialization. It will project on the likelihood of 3-D integration of memory and logic, flash stacking, and other key directions.